Re: RFC on drivers/memory vs drivers/edac memory mapping for DDR Controller

[Shenhar, Talel]

On 1/2/2023 3:43 PM, Borislav Petkov wrote:
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> On Mon, Jan 02, 2023 at 02:17:24PM +0200, Shenhar, Talel wrote:
> > * We want to introduce driver that reads DDR controller RAS register and
> > notify for ECC errors by using EDAC MC API found in drivers/edac.
> > * We also want to have a capability to dynamically change DDR refresh rate
> > based on thermal values (best to be done in drivers/memory ?).
> Is there any particular reason to want to report the errors through EDAC?
>
> Or can't you simply read the RAS register in your memory driver and dump error
> info from there so that you have a single driver that does it all?

Doesn't it go against the MC EDAC concept...?

Reinventing the wheel is something that usually doesn't end well. (I 
could probably list them but guess that as the EDAC maintainer you can 
do it better than me :)  )

I would probably consider the other way around - take the refresh-rate 
driver inside the MC driver as the refresh-rate does not use any 
"memory" framework under drivers/memory.

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>      Boris.
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