Re: [PATCH] locking/qspinlock: Optimize pending state waiting for unlock

[Ingo Molnar]

* Guo Ren <guoren@xxxxxxxxxx> wrote:

> > >> The situation is the SMT scenarios in the same core. Not an entering
> > >> low-power state situation. Of course, the granularity between cores is
> > >> "cacheline", but the granularity between SMT hw threads of the same
> > >> core could be "byte" which internal LSU handles. For example, when a
> > >> hw-thread yields the resources of the core to other hw-threads, this
> > >> patch could help the hw-thread stay in the sleep state and prevent it
> > >> from being woken up by other hw-threads xchg_tail.
> > >>
> > >> Finally, from the software semantic view, does the patch make it more
> > >> accurate? (We don't care about the tail here.)
> > >
> > > Thanks for the clarification.
> > >
> > > I am not arguing for the simplification part. I just want to clarify
> > > my limited understanding of how the CPU hardware are actually dealing
> > > with these conditions.
> > >
> > > With that, I am fine with this patch. It would be nice if you can
> > > elaborate a bit more in your commit log.
> > >
> > > Acked-by: Waiman Long <longman@xxxxxxxxxx>
> > >
> > BTW, have you actually observe any performance improvement with this patch?
> Not yet. I'm researching how the hardware could satisfy qspinlock
> better. Here are three points I concluded:
>  1. Atomic forward progress guarantee: Prevent unnecessary LL/SC
> retry, which may cause expensive bus transactions when crossing the
> NUMA nodes.
>  2. Sub-word atomic primitive: Enable freedom from interference
> between locked, pending, and tail.
>  3. Load-cond primitive: Prevent processor from wasting loop
> operations for detection.

As to this patch, please send a -v2 version of this patch that has this 
discussion & explanation included in the changelog, as requested by Waiman.

Thanks,

	Ingo