On Fri, Jan 06, 2023 at 12:08:03PM -0800, William Zhang wrote:My understanding of combining the spi transfer in the core level does not quite work out to our controller. For example, for a spi message with three transfers, tx, tx and rx. We can possibly combine them in single duplex tx/rx transfer in the core. But this will be treated as duplex transaction in our controller level which require tx and rx data happens at the same time. Obviously this won't work when rx depends on tx happening first. We can not differentiate this combined duplex transfer from the true duplex transfer unless there is some flag to indicate that. Also there is limit of max tx length as the prepend buffer so maybe another parameter. And another reason to be done in the driver level is this prepend mode has dependency on dummy cs workaround which is driver level parameter currently. I am not sure how practical and useful this is to factor them out to the core level? Maybe I didn't fully understand your comments and appreciate if you can elaborate or point me to the related core code.
Multiple transfers within a SPI message may be combined into one
transfer to the controller using its prepend feature. A SPI message is
prependable only if the following are all true:
* One or more half duplex write transfer
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
There is nothing driver specific here, this should be implemented in the
core - we have existing logic to rewrite messages to match driver
constraints, this could be added there possibly with flags to allow
drivers to disable or enable the merging if they've got special
requirements.
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