Re: [PATCH v5 04/10] mfd: intel-m10-bmc: Support multiple CSR register layouts

[Lee Jones]

On Mon, 26 Dec 2022, Ilpo Järvinen wrote:

> There are different addresses for the MAX10 CSR registers. Introducing
> a new data structure m10bmc_csr_map for the register definition of
> MAX10 CSR.
> 
> Provide the csr_map for SPI.
> 
> Co-developed-by: Tianfei zhang <tianfei.zhang@xxxxxxxxx>
> Signed-off-by: Tianfei zhang <tianfei.zhang@xxxxxxxxx>
> Reviewed-by: Russ Weight <russell.h.weight@xxxxxxxxx>
> Reviewed-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> ---
>  drivers/fpga/intel-m10-bmc-sec-update.c | 73 +++++++++++++++++--------
>  drivers/mfd/intel-m10-bmc-core.c        | 10 ++--
>  drivers/mfd/intel-m10-bmc-spi.c         | 24 ++++++++
>  include/linux/mfd/intel-m10-bmc.h       | 39 +++++++++++--
>  4 files changed, 113 insertions(+), 33 deletions(-)

For my own reference (apply this as-is to your sign-off block):

Acked-for-MFD-by: Lee Jones <lee@xxxxxxxxxx>

-- 
Lee Jones [李琼斯]