RE: [PATCH -next 1/2] i2c: designware: Switch from using MMIO access to SMN access
From: Limonciello, Mario
Date: Mon Jan 16 2023 - 11:35:29 EST
[Public]
> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> Sent: Monday, January 16, 2023 06:39
> To: Jan Dąbroś <jsd@xxxxxxxxxxxx>
> Cc: Borislav Petkov <bp@xxxxxxxxx>; Limonciello, Mario
> <Mario.Limonciello@xxxxxxx>; Borislav Petkov <bp@xxxxxxx>; Hans de
> Goede <hdegoede@xxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx; linux-
> i2c@xxxxxxxxxxxxxxx; jarkko.nikula@xxxxxxxxxxxxxxx; wsa@xxxxxxxxxx;
> rrangel@xxxxxxxxxxxx; upstream@xxxxxxxxxxxx; M K, Muralidhara
> <Muralidhara.MK@xxxxxxx>; Chatradhi, Naveen Krishna
> <NaveenKrishna.Chatradhi@xxxxxxx>; Ghannam, Yazen
> <Yazen.Ghannam@xxxxxxx>
> Subject: Re: [PATCH -next 1/2] i2c: designware: Switch from using MMIO
> access to SMN access
>
> On Mon, Jan 16, 2023 at 11:19:00AM +0100, Jan Dąbroś wrote:
> > Hi Borislav,
> >
> > > Make init_amd_nbs() arch_initcall_sync() so that it executes after PCI
> init.
> >
> > I described earlier in this thread why such option is not working -
> > let me quote myself:
> >
> > It's not enough for running init_amd_nbs() to have only
> > pci_arch_init() done. We need the pci bus to be created and registered
> > with all devices found on the bus. We are traversing through them and
> > trying to find northbridge VID/DID. Due to the above, we need to run
> > init_amd_nbs() only after acpi_scan_init() that is invoked from
> > acpi_init() which is registered as subsys_initcall. That's why the
> > trick with switching init_amd_nbs() to arch_initcall_sync will not
> > work.
> >
> > We have a kind of chicken-and-egg problem here. Or is there something I
> missed?
> >
> > I wonder if there is upstreamable option to control order of the
> > drivers' init by forcing link order?
>
> But what exactly do you need from North Bridge? Is it only its existence or
> do you need to have fully instantiated PCI device (if so, why?)?
>
There is a need to be able to write and read PCI config space.