[PATCH] amd/dcn20: Fix high mem clock with multiple displays

[Nicu Borta]

On RX5000 series GPUs, using a high refresh rate monitor causes the VRAM to
always stay at the highest clock (according to AMD, this is done to prevent
flickering).

However, when using 2 monitors (e.g. one at 165Hz and another at 60Hz), then
disconnecting the high refresh monitor, before this patch the VRAM clock didn't
decrease like it should.

This patch fixes that bug, and now, when disconnecting the high refresh rate
monitor, the VRAM clock jumps to the minimum.

Tested for a few months, I haven't noticed any visual artifacts or other errors
(RX5700XT).

Signed-off-by: Nicu Borta <nicuborta123@xxxxxxxxx>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 8a0dd0d7134b..481a15b02126 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -714,7 +714,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
-- 
2.38.2