Re: [RFC v4 5/5] arm: dts: msm: Add multiport controller node for usb

[Krishna Kurapati PSSNV]

On 1/18/2023 11:58 PM, Bjorn Andersson wrote:
> On Sun, Jan 15, 2023 at 05:11:46PM +0530, Krishna Kurapati wrote:
> > Add USB and DWC3 node for teritiary port of SC8280 along
> > with multiport IRQ's and phy's.
>
> Very nice.
>
> Please make the subject prefix "arm64: dts: qcom: sc8280xp:", to match
> other changes in the sc8280xp.dtsi.
> > Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 49 +++++++++++++++++++
> >   arch/arm64/boot/dts/qcom/sc8280xp.dtsi   | 60 ++++++++++++++++++++++++
> >   2 files changed, 109 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > index 84cb6f3eeb56..f9eb854c3444 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > @@ -422,6 +422,20 @@ &usb_1_qmpphy {
> >   	status = "okay";
> >   };
> >   
> > +&usb_2 {
> > +	status = "okay";
>
> Please the status property last in the node.
>
> > +
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&usb2_en_state>,
> > +			<&usb3_en_state>,
> > +			<&usb4_en_state>,
> > +			<&usb5_en_state>;
> > +};
> > +
> > +&usb_2_dwc3 {
> > +	dr_mode = "host";
> > +};
> > +
> >   &usb_2_hsphy0 {
> >   	vdda-pll-supply = <&vreg_l5a>;
> >   	vdda18-supply = <&vreg_l7g>;
> > @@ -472,6 +486,41 @@ &xo_board_clk {
> >   	clock-frequency = <38400000>;
> >   };
> >   
> > +/* PINCTRL */
>
> No need to repeat this comment, its purpose is to indicate that nodes
> above are sorted alphabetically and pinctrl-related nodes are kept here
> at the end of the file. Please place your nodes below the existing /*
> PINCTRL */ comment below.
>
> Thanks,
> Bjorn
>
> > +&pm8450c_gpios {
> > +	usb2_en_state: usb2-en-state {
> > +		pins = "gpio9";
> > +		function = "normal";
> > +		output-high;
> > +		power-source = <0>;
> > +	};
> > +};
> > +
> > +&pm8450e_gpios {
> > +	usb3_en_state: usb3-en-state {
> > +		pins = "gpio5";
> > +		function = "normal";
> > +		output-high;
> > +		power-source = <0>;
> > +	};
> > +};
> > +
> > +&pm8450g_gpios {
> > +	usb4_en_state: usb4-en-state {
> > +		pins = "gpio5";
> > +		function = "normal";
> > +		output-high;
> > +		power-source = <0>;
> > +	};
> > +
> > +	usb5_en_state: usb5-en-state {
> > +		pins = "gpio9";
> > +		function = "normal";
> > +		output-high;
> > +		power-source = <0>;
> > +	};
> > +};
> > +
> >   /* PINCTRL */
> >   
> >   &tlmm {
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 109c9d2b684d..e9866ab5c6e2 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -1969,6 +1969,66 @@ usb_1_dwc3: usb@a800000 {
> >   			};
> >   		};
> >   
> > +		usb_2: usb@a4f8800 {
> > +			compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
> > +			reg = <0 0x0a4f8800 0 0x400>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> > +				 <&gcc GCC_USB30_MP_MASTER_CLK>,
> > +				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> > +				 <&gcc GCC_USB30_MP_SLEEP_CLK>,
> > +				 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > +				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> > +				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> > +				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> > +				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> > +			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
> > +				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
> > +
> > +			assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > +					  <&gcc GCC_USB30_MP_MASTER_CLK>;
> > +			assigned-clock-rates = <19200000>, <200000000>;
> > +
> > +			interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
> > +						<&pdc 126 IRQ_TYPE_EDGE_RISING>,
> > +						<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +			interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
> > +						"ss_phy_irq";
> > +
> > +			power-domains = <&gcc USB30_MP_GDSC>;
> > +
> > +			resets = <&gcc GCC_USB30_MP_BCR>;
> > +
> > +			interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
> > +					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
> > +			interconnect-names = "usb-ddr", "apps-usb";
> > +
> > +			required-opps = <&rpmhpd_opp_nom>;
> > +
> > +			status = "disabled";
> > +
> > +			usb_2_dwc3: usb@a400000 {
> > +				compatible = "snps,dwc3";
> > +				reg = <0 0x0a400000 0 0xcd00>;
> > +				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> > +				iommus = <&apps_smmu 0x800 0x0>;
> > +				num-ports = <4>;
> > +				num-ss-ports = <2>;
> > +				phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
> > +					<&usb_2_hsphy1>, <&usb_2_qmpphy1>,
> > +					<&usb_2_hsphy2>,
> > +					<&usb_2_hsphy3>;
> > +				phy-names = "usb2-phy_port0", "usb3-phy_port0",
> > +						"usb2-phy_port1", "usb3-phy_port1",
> > +						"usb2-phy_port2",
> > +						"usb2-phy_port3";
> > +			};
> > +		};
> > +
> >   		pdc: interrupt-controller@b220000 {
> >   			compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
> >   			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> > --
> > 2.39.0

Hi Bjorn,

 Thanks for the review. Will make sure to incorporate these changes in 
the next version.

Regards,
Krishna,