Re: [PATCH v2 15/19] clk: imx6ul: fix enet1 gate configuration

[Abel Vesa]

On 23-01-30 13:15:30, Oleksij Rempel wrote:
> On Sun, Jan 29, 2023 at 07:32:31PM +0200, Abel Vesa wrote:
> > On 23-01-17 07:14:49, Oleksij Rempel wrote:
> > > According to the "i.MX 6UltraLite Applications Processor Reference Manual,
> > > Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
> > > of PLL6. It is controlling ENET1 separately.
> > > 
> > > So, instead of this picture (implementation before this patch):
> > > fec1 <- enet_ref (divider) <---------------------------,
> > >                                                        |- pll6_enet (gate)
> > > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
> > > 
> > > we should have this one (after this patch):
> > > fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
> > >                                                        |- pll6_enet
> > > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
> > > 
> > > With this fix, the RMII reference clock will be turned off, after
> > > setting network interface down on each separate interface
> > > (ip l s dev eth0 down). Which was not working before, on system with both
> > > FECs enabled.
> > > 
> > > Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
> > 
> > I'm OK with this. Maybe a fixes tag ?
> 
> Hm. Initial commit was:
> Fixes: 787b4271a6a0 ("clk: imx: add imx6ul clk tree support")
> but this patch will not apply on top of it.
> Next possible commit would be:
> Fixes: 1487b60dc2d2 ("clk: imx6ul: Switch to clk_hw based API")
> But this patch didn't introduce this issue, it was just refactoring.

Hm, in that case I don't think is qoing to be backported ever.

> 
> What do you prefer?

I'll apply it as it is.

Thanks.

> 
> Regards,
> Oleksij
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