Re: [PATCH 1/2] KVM: nVMX: Move EVMCS1_SUPPORT_* macros to hyperv.c

From: Vitaly Kuznetsov
Date: Thu Feb 09 2023 - 08:09:47 EST

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In reply to: Sean Christopherson: "[PATCH 1/2] KVM: nVMX: Move EVMCS1_SUPPORT_* macros to hyperv.c"
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Sean Christopherson <seanjc@xxxxxxxxxx> writes:

> Move the macros that define the set of VMCS controls that are supported
> by eVMCS1 from hyperv.h to hyperv.c, i.e. make them "private". The
> macros should never be consumed directly by KVM at-large since the "final"
> set of supported controls depends on guest CPUID.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
> ---
> arch/x86/kvm/vmx/hyperv.c | 105 ++++++++++++++++++++++++++++++++++++++
> arch/x86/kvm/vmx/hyperv.h | 105 --------------------------------------
> 2 files changed, 105 insertions(+), 105 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx/hyperv.c b/arch/x86/kvm/vmx/hyperv.c
> index 22daca752797..b6748055c586 100644
> --- a/arch/x86/kvm/vmx/hyperv.c
> +++ b/arch/x86/kvm/vmx/hyperv.c
> @@ -13,6 +13,111 @@
>
> #define CC KVM_NESTED_VMENTER_CONSISTENCY_CHECK
>
> +/*
> + * Enlightened VMCSv1 doesn't support these:
> + *
> + * POSTED_INTR_NV = 0x00000002,
> + * GUEST_INTR_STATUS = 0x00000810,
> + * APIC_ACCESS_ADDR = 0x00002014,
> + * POSTED_INTR_DESC_ADDR = 0x00002016,
> + * EOI_EXIT_BITMAP0 = 0x0000201c,
> + * EOI_EXIT_BITMAP1 = 0x0000201e,
> + * EOI_EXIT_BITMAP2 = 0x00002020,
> + * EOI_EXIT_BITMAP3 = 0x00002022,
> + * GUEST_PML_INDEX = 0x00000812,
> + * PML_ADDRESS = 0x0000200e,
> + * VM_FUNCTION_CONTROL = 0x00002018,
> + * EPTP_LIST_ADDRESS = 0x00002024,
> + * VMREAD_BITMAP = 0x00002026,
> + * VMWRITE_BITMAP = 0x00002028,
> + *
> + * TSC_MULTIPLIER = 0x00002032,
> + * PLE_GAP = 0x00004020,
> + * PLE_WINDOW = 0x00004022,
> + * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
> + *
> + * Currently unsupported in KVM:
> + * GUEST_IA32_RTIT_CTL = 0x00002814,
> + */
> +#define EVMCS1_SUPPORTED_PINCTRL \
> + (PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
> + PIN_BASED_EXT_INTR_MASK | \
> + PIN_BASED_NMI_EXITING | \
> + PIN_BASED_VIRTUAL_NMIS)
> +
> +#define EVMCS1_SUPPORTED_EXEC_CTRL \
> + (CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
> + CPU_BASED_HLT_EXITING | \
> + CPU_BASED_CR3_LOAD_EXITING | \
> + CPU_BASED_CR3_STORE_EXITING | \
> + CPU_BASED_UNCOND_IO_EXITING | \
> + CPU_BASED_MOV_DR_EXITING | \
> + CPU_BASED_USE_TSC_OFFSETTING | \
> + CPU_BASED_MWAIT_EXITING | \
> + CPU_BASED_MONITOR_EXITING | \
> + CPU_BASED_INVLPG_EXITING | \
> + CPU_BASED_RDPMC_EXITING | \
> + CPU_BASED_INTR_WINDOW_EXITING | \
> + CPU_BASED_CR8_LOAD_EXITING | \
> + CPU_BASED_CR8_STORE_EXITING | \
> + CPU_BASED_RDTSC_EXITING | \
> + CPU_BASED_TPR_SHADOW | \
> + CPU_BASED_USE_IO_BITMAPS | \
> + CPU_BASED_MONITOR_TRAP_FLAG | \
> + CPU_BASED_USE_MSR_BITMAPS | \
> + CPU_BASED_NMI_WINDOW_EXITING | \
> + CPU_BASED_PAUSE_EXITING | \
> + CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
> +
> +#define EVMCS1_SUPPORTED_2NDEXEC \
> + (SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
> + SECONDARY_EXEC_WBINVD_EXITING | \
> + SECONDARY_EXEC_ENABLE_VPID | \
> + SECONDARY_EXEC_ENABLE_EPT | \
> + SECONDARY_EXEC_UNRESTRICTED_GUEST | \
> + SECONDARY_EXEC_DESC | \
> + SECONDARY_EXEC_ENABLE_RDTSCP | \
> + SECONDARY_EXEC_ENABLE_INVPCID | \
> + SECONDARY_EXEC_XSAVES | \
> + SECONDARY_EXEC_RDSEED_EXITING | \
> + SECONDARY_EXEC_RDRAND_EXITING | \
> + SECONDARY_EXEC_TSC_SCALING | \
> + SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
> + SECONDARY_EXEC_PT_USE_GPA | \
> + SECONDARY_EXEC_PT_CONCEAL_VMX | \
> + SECONDARY_EXEC_BUS_LOCK_DETECTION | \
> + SECONDARY_EXEC_NOTIFY_VM_EXITING | \
> + SECONDARY_EXEC_ENCLS_EXITING)
> +
> +#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
> +
> +#define EVMCS1_SUPPORTED_VMEXIT_CTRL \
> + (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | \
> + VM_EXIT_SAVE_DEBUG_CONTROLS | \
> + VM_EXIT_ACK_INTR_ON_EXIT | \
> + VM_EXIT_HOST_ADDR_SPACE_SIZE | \
> + VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
> + VM_EXIT_SAVE_IA32_PAT | \
> + VM_EXIT_LOAD_IA32_PAT | \
> + VM_EXIT_SAVE_IA32_EFER | \
> + VM_EXIT_LOAD_IA32_EFER | \
> + VM_EXIT_CLEAR_BNDCFGS | \
> + VM_EXIT_PT_CONCEAL_PIP | \
> + VM_EXIT_CLEAR_IA32_RTIT_CTL)
> +
> +#define EVMCS1_SUPPORTED_VMENTRY_CTRL \
> + (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | \
> + VM_ENTRY_LOAD_DEBUG_CONTROLS | \
> + VM_ENTRY_IA32E_MODE | \
> + VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
> + VM_ENTRY_LOAD_IA32_PAT | \
> + VM_ENTRY_LOAD_IA32_EFER | \
> + VM_ENTRY_LOAD_BNDCFGS | \
> + VM_ENTRY_PT_CONCEAL_PIP | \
> + VM_ENTRY_LOAD_IA32_RTIT_CTL)
> +
> +#define EVMCS1_SUPPORTED_VMFUNC (0)
> +
> DEFINE_STATIC_KEY_FALSE(enable_evmcs);
>
> #define EVMCS1_OFFSET(x) offsetof(struct hv_enlightened_vmcs, x)
> diff --git a/arch/x86/kvm/vmx/hyperv.h b/arch/x86/kvm/vmx/hyperv.h
> index 78d17667e7ec..1299143d00df 100644
> --- a/arch/x86/kvm/vmx/hyperv.h
> +++ b/arch/x86/kvm/vmx/hyperv.h
> @@ -22,111 +22,6 @@ DECLARE_STATIC_KEY_FALSE(enable_evmcs);
>
> #define KVM_EVMCS_VERSION 1
>
> -/*
> - * Enlightened VMCSv1 doesn't support these:
> - *
> - * POSTED_INTR_NV = 0x00000002,
> - * GUEST_INTR_STATUS = 0x00000810,
> - * APIC_ACCESS_ADDR = 0x00002014,
> - * POSTED_INTR_DESC_ADDR = 0x00002016,
> - * EOI_EXIT_BITMAP0 = 0x0000201c,
> - * EOI_EXIT_BITMAP1 = 0x0000201e,
> - * EOI_EXIT_BITMAP2 = 0x00002020,
> - * EOI_EXIT_BITMAP3 = 0x00002022,
> - * GUEST_PML_INDEX = 0x00000812,
> - * PML_ADDRESS = 0x0000200e,
> - * VM_FUNCTION_CONTROL = 0x00002018,
> - * EPTP_LIST_ADDRESS = 0x00002024,
> - * VMREAD_BITMAP = 0x00002026,
> - * VMWRITE_BITMAP = 0x00002028,
> - *
> - * TSC_MULTIPLIER = 0x00002032,
> - * PLE_GAP = 0x00004020,
> - * PLE_WINDOW = 0x00004022,
> - * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
> - *
> - * Currently unsupported in KVM:
> - * GUEST_IA32_RTIT_CTL = 0x00002814,
> - */
> -#define EVMCS1_SUPPORTED_PINCTRL \
> - (PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
> - PIN_BASED_EXT_INTR_MASK | \
> - PIN_BASED_NMI_EXITING | \
> - PIN_BASED_VIRTUAL_NMIS)
> -
> -#define EVMCS1_SUPPORTED_EXEC_CTRL \
> - (CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | \
> - CPU_BASED_HLT_EXITING | \
> - CPU_BASED_CR3_LOAD_EXITING | \
> - CPU_BASED_CR3_STORE_EXITING | \
> - CPU_BASED_UNCOND_IO_EXITING | \
> - CPU_BASED_MOV_DR_EXITING | \
> - CPU_BASED_USE_TSC_OFFSETTING | \
> - CPU_BASED_MWAIT_EXITING | \
> - CPU_BASED_MONITOR_EXITING | \
> - CPU_BASED_INVLPG_EXITING | \
> - CPU_BASED_RDPMC_EXITING | \
> - CPU_BASED_INTR_WINDOW_EXITING | \
> - CPU_BASED_CR8_LOAD_EXITING | \
> - CPU_BASED_CR8_STORE_EXITING | \
> - CPU_BASED_RDTSC_EXITING | \
> - CPU_BASED_TPR_SHADOW | \
> - CPU_BASED_USE_IO_BITMAPS | \
> - CPU_BASED_MONITOR_TRAP_FLAG | \
> - CPU_BASED_USE_MSR_BITMAPS | \
> - CPU_BASED_NMI_WINDOW_EXITING | \
> - CPU_BASED_PAUSE_EXITING | \
> - CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
> -
> -#define EVMCS1_SUPPORTED_2NDEXEC \
> - (SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
> - SECONDARY_EXEC_WBINVD_EXITING | \
> - SECONDARY_EXEC_ENABLE_VPID | \
> - SECONDARY_EXEC_ENABLE_EPT | \
> - SECONDARY_EXEC_UNRESTRICTED_GUEST | \
> - SECONDARY_EXEC_DESC | \
> - SECONDARY_EXEC_ENABLE_RDTSCP | \
> - SECONDARY_EXEC_ENABLE_INVPCID | \
> - SECONDARY_EXEC_XSAVES | \
> - SECONDARY_EXEC_RDSEED_EXITING | \
> - SECONDARY_EXEC_RDRAND_EXITING | \
> - SECONDARY_EXEC_TSC_SCALING | \
> - SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
> - SECONDARY_EXEC_PT_USE_GPA | \
> - SECONDARY_EXEC_PT_CONCEAL_VMX | \
> - SECONDARY_EXEC_BUS_LOCK_DETECTION | \
> - SECONDARY_EXEC_NOTIFY_VM_EXITING | \
> - SECONDARY_EXEC_ENCLS_EXITING)
> -
> -#define EVMCS1_SUPPORTED_3RDEXEC (0ULL)
> -
> -#define EVMCS1_SUPPORTED_VMEXIT_CTRL \
> - (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | \
> - VM_EXIT_SAVE_DEBUG_CONTROLS | \
> - VM_EXIT_ACK_INTR_ON_EXIT | \
> - VM_EXIT_HOST_ADDR_SPACE_SIZE | \
> - VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
> - VM_EXIT_SAVE_IA32_PAT | \
> - VM_EXIT_LOAD_IA32_PAT | \
> - VM_EXIT_SAVE_IA32_EFER | \
> - VM_EXIT_LOAD_IA32_EFER | \
> - VM_EXIT_CLEAR_BNDCFGS | \
> - VM_EXIT_PT_CONCEAL_PIP | \
> - VM_EXIT_CLEAR_IA32_RTIT_CTL)
> -
> -#define EVMCS1_SUPPORTED_VMENTRY_CTRL \
> - (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | \
> - VM_ENTRY_LOAD_DEBUG_CONTROLS | \
> - VM_ENTRY_IA32E_MODE | \
> - VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
> - VM_ENTRY_LOAD_IA32_PAT | \
> - VM_ENTRY_LOAD_IA32_EFER | \
> - VM_ENTRY_LOAD_BNDCFGS | \
> - VM_ENTRY_PT_CONCEAL_PIP | \
> - VM_ENTRY_LOAD_IA32_RTIT_CTL)
> -
> -#define EVMCS1_SUPPORTED_VMFUNC (0)
> -
> struct evmcs_field {
> u16 offset;
> u16 clean_field;

Reviewed-by: Vitaly Kuznetsov <vkuznets@xxxxxxxxxx>

--
Vitaly

Next message: Mike Rapoport: "Re: [PATCH] mm/doc: Replace isolate_lru_page with folio_isolate_lru"
Previous message: Daniel Bristot de Oliveira: "Re: [RFC PATCH v2] sched/deadline: Add more reschedule cases to prio_changed_dl()"
In reply to: Sean Christopherson: "[PATCH 1/2] KVM: nVMX: Move EVMCS1_SUPPORT_* macros to hyperv.c"
Next in thread: Sean Christopherson: "[PATCH 2/2] KVM: VMX: Stub out enable_evmcs static key for CONFIG_HYPERV=n"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]