[PATCH v2 4/4] arm64: dts: qcom: sa8775p: add the BT high-speed UART for sa8775p-ride
From: Bartosz Golaszewski
Date: Wed Feb 15 2023 - 10:40:29 EST
From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
Add the serial port connected to the Bluetooth controller on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 17 ++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 47cf26ea49e8..e7629cb0306c 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -14,6 +14,7 @@ / {
aliases {
serial0 = &uart10;
serial1 = &uart12;
+ serial2 = &uart17;
i2c18 = &i2c18;
spi16 = &spi16;
};
@@ -89,6 +90,29 @@ qup_uart12_tx: qup_uart12_tx-state {
qup_uart12_rx: qup_uart12_rx-state {
pins = "gpio55";
function = "qup1_se5";
+ };
+
+ qup_uart17_cts: qup-uart17-cts-state {
+ pins = "gpio91";
+ function = "qup2_se3";
+ bias-disable;
+ };
+
+ qup_uart17_rts: qup0_uart17_rts-state {
+ pins = "gpio92";
+ function = "qup2_se3";
+ bias-pull-down;
+ };
+
+ qup_uart17_tx: qup0_uart17_tx-state {
+ pins = "gpio93";
+ function = "qup2_se3";
+ bias-pull-up;
+ };
+
+ qup_uart17_rx: qup0_uart17_rx-state {
+ pins = "gpio94";
+ function = "qup2_se3";
bias-pull-down;
};
};
@@ -109,6 +133,15 @@ &uart12 {
status = "okay";
};
+&uart17 {
+ pinctrl-0 = <&qup_uart17_cts>,
+ <&qup_uart17_rts>,
+ <&qup_uart17_tx>,
+ <&qup_uart17_rx>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 8b8931ea739d..9e057a34b14f 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -539,6 +539,23 @@ &config_noc SLAVE_QUP_2 0>,
status = "disabled";
};
+ uart17: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x88c000 0x0 0x4000>;
+ interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+ &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x890000 0x0 0x4000>;
--
2.37.2