Re: [PATCH 2/7] PCI: qcom: Add IPQ9574 PCIe support

[Sricharan Ramabadhran]

Hi Devi,

On 2/14/2023 10:11 PM, Devi Priya wrote:
> Adding PCIe support for IPQ9574 SoC
>
> Co-developed-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
> Signed-off-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
> Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
> ---
>   drivers/pci/controller/dwc/pcie-qcom.c | 119 +++++++++++++++++++++++++
>   1 file changed, 119 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a232b04af048..57606c113d45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -193,6 +193,12 @@ struct qcom_pcie_resources_2_9_0 {
>   	struct reset_control *rst;
>   };
>   
> +struct qcom_pcie_resources_1_27_0 {
> +	struct clk_bulk_data *clks;
> +	struct reset_control *rst;
> +	int num_clks;
> +};
> +
>   union qcom_pcie_resources {
>   	struct qcom_pcie_resources_1_0_0 v1_0_0;
>   	struct qcom_pcie_resources_2_1_0 v2_1_0;
> @@ -201,6 +207,7 @@ union qcom_pcie_resources {
>   	struct qcom_pcie_resources_2_4_0 v2_4_0;
>   	struct qcom_pcie_resources_2_7_0 v2_7_0;
>   	struct qcom_pcie_resources_2_9_0 v2_9_0;
> +	struct qcom_pcie_resources_1_27_0 v1_27_0;
>   };
>   
>   struct qcom_pcie;
> @@ -1409,6 +1416,104 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
>   	return 0;
>   }
>   
> +static int qcom_pcie_get_resources_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
> +	if (res->clks < 0)
> +		return res->num_clks;
> +
> +	res->rst = devm_reset_control_array_get_exclusive(dev);
> +	if (IS_ERR(res->rst))
> +		return PTR_ERR(res->rst);
> +
> +	return 0;
> +}
> +
> +static void qcom_pcie_deinit_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +
> +	clk_bulk_disable_unprepare(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct qcom_pcie_resources_1_27_0 *res = &pcie->res.v1_27_0;
> +	struct device *dev = pcie->pci->dev;
> +	int ret;
> +
> +	ret = reset_control_assert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset assert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	/*
> +	 * Delay periods before and after reset deassert are working values
> +	 * from downstream Codeaurora kernel
> +	 */
> +	usleep_range(2000, 2500);
> +
> +	ret = reset_control_deassert(res->rst);
> +	if (ret) {
> +		dev_err(dev, "reset deassert failed (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	usleep_range(2000, 2500);
> +
> +	return clk_bulk_prepare_enable(res->num_clks, res->clks);
> +}
> +
> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
> +{
> +	struct dw_pcie *pci = pcie->pci;
> +	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	u32 val;
> +	int i;
> +
> +	writel(0x8000000, pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
> +
> +	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> +	val &= ~BIT(0);
> +	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
> +
> +	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
> +	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
> +	       pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
> +	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
> +	       GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
> +	       pci->dbi_base + GEN3_RELATED_OFF);
> +
> +	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
> +	       SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
> +	       AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
> +	       pcie->parf + PCIE20_PARF_SYS_CTRL);
> +
> +	writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
> +
> +	dw_pcie_dbi_ro_wr_en(pci);
> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +
> +	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +	val &= ~PCI_EXP_LNKCAP_ASPMS;
> +	writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
> +
> +	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> +	       PCI_EXP_DEVCTL2);
> +
> +	for (i = 0; i < 256; i++)
> +		writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
> +
> +	return 0;
> +}
> +
>   static int qcom_pcie_link_up(struct dw_pcie *pci)
>   {
>   	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -1620,6 +1725,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
>   	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
>   };
>   
> +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */
> +static const struct qcom_pcie_ops ops_1_27_0 = {
> +	.get_resources = qcom_pcie_get_resources_1_27_0,
> +	.init = qcom_pcie_init_1_27_0,
> +	.post_init = qcom_pcie_post_init_1_27_0,
> +	.deinit = qcom_pcie_deinit_1_27_0,
> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> +};
> +
>   static const struct qcom_pcie_cfg cfg_1_0_0 = {
>   	.ops = &ops_1_0_0,
>   };
> @@ -1652,6 +1766,10 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>   	.ops = &ops_2_9_0,
>   };
>   
> +static const struct qcom_pcie_cfg cfg_1_27_0 = {
> +	.ops = &ops_1_27_0,
> +};
> +
>   static const struct dw_pcie_ops dw_pcie_ops = {
>   	.link_up = qcom_pcie_link_up,
>   	.start_link = qcom_pcie_start_link,
> @@ -1829,6 +1947,7 @@ static const struct of_device_id qcom_pcie_match[] = {
>   	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
>   	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
>   	{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
> +	{ .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 },

  I do not see much difference between 2_9_0 and 1_27_0. Is this patch
  really required. Can you check if it works with 2_9_0 itself ?

Regards,
 Sricharan