Re: [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver

[Hal Feng]

On Sun, 19 Feb 2023 22:23:39 +0100, Emil Renner Berthing wrote:
> On Tue, 20 Dec 2022 at 01:51, Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> wrote:
>> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> new file mode 100644
>> index 000000000000..abc1c280bbe3
>> --- /dev/null
>> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> @@ -0,0 +1,448 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * StarFive JH7110 System Clock Driver
[...]
>> +static int __init jh7110_syscrg_probe(struct platform_device *pdev)
>> +{
>> +       struct jh71x0_clk_priv *priv;
>> +       unsigned int idx;
>> +       int ret;
>> +
>> +       priv = devm_kzalloc(&pdev->dev,
>> +                           struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT),
>> +                           GFP_KERNEL);
>> +       if (!priv)
>> +               return -ENOMEM;
>> +
>> +       spin_lock_init(&priv->rmw_lock);
>> +       priv->dev = &pdev->dev;
>> +       priv->base = devm_platform_ioremap_resource(pdev, 0);
>> +       if (IS_ERR(priv->base))
>> +               return PTR_ERR(priv->base);
>> +
>> +       dev_set_drvdata(priv->dev, priv->base);
>> +
>> +       /* 24MHz -> 1250.0MHz */
>> +       priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
>> +                                                        "osc", 0, 625, 12);
>> +       if (IS_ERR(priv->pll[0]))
>> +               return PTR_ERR(priv->pll[0]);
> 
> Hi Hal,
> 
> Are you sure this should be 1.25GHz and not 1GHz? I can't seem to make
> the ethernet driver work unless I set it to 1GHz. This also makes
> other derived clocks that should be 125MHz show up as such in the
> clock tree. Eg. "usb_125m".
> 
> Perhaps it's because I updated my board to the latest u-boot
> release[1]. I know these PLLs are just placeholders until you add
> proper code to control them, but until then it's important that these
> values match the defaults or whatever the latest u-boot sets them to.
> Please check the PLLs below with the latest u-boot too.
> 
> /Emil
> 
> [1]: https://github.com/starfive-tech/VisionFive2/releases

After this series sent out, we found a bug in the u-boot when cpu
running at 1.25 GHz, so now the cpu runs at 1GHz in the latest
u-boot. I have updated it in v4. Thanks for reminding.
What's more, we will support adjusting the cpu frequency in the
future, so the cpu can run at a higher frequency.

Best regards,
Hal

> 
>> +       /* 24MHz -> 1066.0MHz */
>> +       priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
>> +                                                        "osc", 0, 533, 12);
>> +       if (IS_ERR(priv->pll[1]))
>> +               return PTR_ERR(priv->pll[1]);
>> +
>> +       /* 24MHz -> 1188.0MHz */
>> +       priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
>> +                                                        "osc", 0, 99, 2);
>> +       if (IS_ERR(priv->pll[2]))
>> +               return PTR_ERR(priv->pll[2]);