Re: [PATCH 2/2] arm64: dts: qcom: sa8775p: add cpufreq node

[Konrad Dybcio]

On 21.02.2023 16:05, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
> 
> Add a node for the cpufreq engine and specify the frequency domains for
> all CPUs.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index ce5976e36aee..5e2bc67b3178 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -37,6 +37,7 @@ CPU0: cpu@0 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  				compatible = "cache";
> @@ -52,6 +53,7 @@ CPU1: cpu@100 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  				compatible = "cache";
> @@ -64,6 +66,7 @@ CPU2: cpu@200 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x200>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			next-level-cache = <&L2_2>;
>  			L2_2: l2-cache {
>  				compatible = "cache";
> @@ -76,6 +79,7 @@ CPU3: cpu@300 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x300>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			next-level-cache = <&L2_3>;
>  			L2_3: l2-cache {
>  				compatible = "cache";
> @@ -88,6 +92,7 @@ CPU4: cpu@10000 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x10000>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			next-level-cache = <&L2_4>;
>  			L2_4: l2-cache {
>  				compatible = "cache";
> @@ -104,6 +109,7 @@ CPU5: cpu@10100 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x10100>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			next-level-cache = <&L2_5>;
>  			L2_5: l2-cache {
>  				compatible = "cache";
> @@ -116,6 +122,7 @@ CPU6: cpu@10200 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x10200>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			next-level-cache = <&L2_6>;
>  			L2_6: l2-cache {
>  				compatible = "cache";
> @@ -128,6 +135,7 @@ CPU7: cpu@10300 {
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x10300>;
>  			enable-method = "psci";
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			next-level-cache = <&L2_7>;
>  			L2_7: l2-cache {
>  				compatible = "cache";
> @@ -731,6 +739,19 @@ tcsr_mutex: hwlock@1f40000 {
>  			#hwlock-cells = <1>;
>  		};
>  
> +		cpufreq_hw: cpufreq@18591000 {
> +			compatible = "qcom,sa8775p-cpufreq-epss",
> +				     "qcom,cpufreq-epss";
That's some very aggressive wrapping! :P

Nevertheless,

Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>

Konrad
> +			reg = <0x0 0x18591000 0x0 0x1000>,
> +			      <0x0 0x18593000 0x0 0x1000>;
> +			reg-names = "freq-domain0", "freq-domain1";
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +
> +			#freq-domain-cells = <1>;
> +		};
> +
>  		tlmm: pinctrl@f000000 {
>  			compatible = "qcom,sa8775p-tlmm";
>  			reg = <0x0 0xf000000 0x0 0x1000000>;