Re: [PATCH v2 1/2] x86/speculation: Allow enabling STIBP with legacy IBRS

[KP Singh]

On Wed, Feb 22, 2023 at 4:24 AM Borislav Petkov <bp@xxxxxxxxx> wrote:
>
> On Tue, Feb 21, 2023 at 07:49:07PM +0100, KP Singh wrote:
> > Setting the IBRS bit implicitly enables STIBP to protect against
> > cross-thread branch target injection. With enhanced IBRS, the bit it set
> > once and is not cleared again. However, on CPUs with just legacy IBRS,
> > IBRS bit set on user -> kernel and cleared on kernel -> user (a.k.a
> > KERNEL_IBRS). Clearing this bit also disables the implicitly enabled
> > STIBP, thus requiring some form of cross-thread protection in userspace.
> >
> > Enable STIBP, either opt-in via prctl or seccomp, or always on depending
> > on the choice of mitigation selected via spectre_v2_user.
> >
> > Reported-by: José Oliveira <joseloliveira11@xxxxxxxxx>
> > Reported-by: Rodrigo Branco <rodrigo@xxxxxxxxxxxxxxxxx>
> > Reviewed-by: Alexandra Sandulescu <aesa@xxxxxxxxxx>
> > Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Signed-off-by: KP Singh <kpsingh@xxxxxxxxxx>
> > ---
> >  arch/x86/kernel/cpu/bugs.c | 33 ++++++++++++++++++++++-----------
> >  1 file changed, 22 insertions(+), 11 deletions(-)
>
> Below is what I'd like to see. Holler if something's wrong.

Thanks for iterating. I think your commit description and rewrite
omits a few key subtleties which I have tried to reinforce in both the
commit log and the comments.

Q: What does STIBP have to do with IBRS?
A: Setting the IBRS bit implicitly enables STIBP / some form of cross
thread protection.

Q: Why does it work with eIBRS?
A: Because we set the IBRS bit once and leave it set when using eIBRS

I think this subtlety should be reinforced in the commit description
and code comments so that we don't get it wrong again. Your commit
does answer this one (thanks!)

Q: Why does it not work with the way the kernel currently implements
legacy IBRS?
A: Because the kernel clears the bit on returning to user space.

>
> It is totally untested ofc.
>
> ---
> From: KP Singh <kpsingh@xxxxxxxxxx>
> Date: Tue, 21 Feb 2023 19:49:07 +0100
> Subject: [PATCH] x86/speculation: Allow enabling STIBP with legacy IBRS
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> When plain IBRS is enabled (not enhanced IBRS), the logic in
> spectre_v2_user_select_mitigation() determines that STIBP is not needed.
>
> However, on return to userspace, the IBRS bit is cleared for performance
> reasons. That leaves userspace threads vulnerable to cross-thread
> predictions influence against which STIBP protects.
>
> Exclude IBRS from the spectre_v2_in_ibrs_mode() check to allow for
> enabling STIBP through seccomp/prctl().
>
>   [ bp: Rewrite commit message and massage. ]
>
> Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS")
> Reported-by: José Oliveira <joseloliveira11@xxxxxxxxx>
> Reported-by: Rodrigo Branco <rodrigo@xxxxxxxxxxxxxxxxx>
> Signed-off-by: KP Singh <kpsingh@xxxxxxxxxx>
> Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
> Link: https://lore.kernel.org/r/20230221184908.2349578-1-kpsingh@xxxxxxxxxx
> ---
>  arch/x86/kernel/cpu/bugs.c | 25 ++++++++++++++++++-------
>  1 file changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> index cf81848b72f4..9a969ab0e62a 100644
> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -1133,14 +1133,18 @@ spectre_v2_parse_user_cmdline(void)
>         return SPECTRE_V2_USER_CMD_AUTO;
>  }
>
> -static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
> +static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
>  {
> -       return mode == SPECTRE_V2_IBRS ||
> -              mode == SPECTRE_V2_EIBRS ||
> +       return mode == SPECTRE_V2_EIBRS ||
>                mode == SPECTRE_V2_EIBRS_RETPOLINE ||
>                mode == SPECTRE_V2_EIBRS_LFENCE;
>  }
>
> +static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
> +{
> +       return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
> +}
> +
>  static void __init
>  spectre_v2_user_select_mitigation(void)
>  {
> @@ -1203,12 +1207,19 @@ spectre_v2_user_select_mitigation(void)
>         }
>
>         /*
> -        * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
> -        * STIBP is not required.
> +        * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
> +        * is not required.
> +        *
> +        * Enhanced IBRS protects also against user-mode attacks as the IBRS bit
> +        * remains always set which implicitly enables cross-thread protections.
> +        * However, in legacy IBRS mode, the IBRS bit is set only on kernel
> +        * entry and cleared on return to userspace. This disables the implicit
> +        * cross-thread protections so allow for STIBP to be selected in that
> +        * case.
>          */
>         if (!boot_cpu_has(X86_FEATURE_STIBP) ||
>             !smt_possible ||
> -           spectre_v2_in_ibrs_mode(spectre_v2_enabled))
> +           spectre_v2_in_eibrs_mode(spectre_v2_enabled))
>                 return;
>
>         /*
> @@ -2340,7 +2351,7 @@ static ssize_t mmio_stale_data_show_state(char *buf)
>
>  static char *stibp_state(void)
>  {
> -       if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
> +       if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))

The reason why I refactored this into a separate helper was to
document the subtleties I mentioned above and anchor them to one place
as the function is used in 2 places. But this is a maintainer's
choice, so it's your call :)

I do agree with Pawan that it's worth adding a pr_info about what the
kernel is doing about STIBP.

- KP

>                 return "";
>
>         switch (spectre_v2_user_stibp) {
> --
> 2.35.1
>
> --
> Regards/Gruss,
>     Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette