[PATCH 0/5] OPP and devfreq for all Adrenos
From: Konrad Dybcio
Date: Wed Feb 22 2023 - 16:47:18 EST
This series is a combination of [1] and a subset of [2] and some new
stuff.
With it, devfreq is used on all a2xx-a6xx (including gmu and
gmu-wrapper) and all clk_set_rate(core clock) calls are dropped in
favour of dev_pm_opp_set_rate, which - drumroll - lets us scale
the voltage domain. DT patches making use of that will be sent
separately.
On top of that, a5xx gets a call to enable icc scaling from the OPP
tables. No SoCs implementing a2xx have icc support yet and a3/4xx
SoCs have separate logic for that, which will be updated at a later
time.
Getting this in for 6.4 early would be appreciated, as that would
allow for getting GMU wrapper GPUs up (without VDD&icc scaling they
can only run at lower freqs, which is.. ehhh..)
Changes:
- a3xx busy: use the _1 counter as per msm-3.x instead of _0
- a6xx-series-opp: basically rewrite, ensure compat with all gens
- a2/4xx busy: new patch
- a5xx icc: new patch
[1] https://lore.kernel.org/linux-arm-msm/20230130093809.2079314-1-konrad.dybcio@xxxxxxxxxx/
[2] https://lore.kernel.org/linux-arm-msm/20230214173145.2482651-1-konrad.dybcio@xxxxxxxxxx/
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
Konrad Dybcio (5):
drm/msm/adreno: Use OPP for every GPU generation
drm/msm/a2xx: Implement .gpu_busy
drm/msm/a3xx: Implement .gpu_busy
drm/msm/a4xx: Implement .gpu_busy
drm/msm/a5xx: Enable optional icc voting from OPP tables
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 ++++
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 ++++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 94 +++++++++++++++------------------
drivers/gpu/drm/msm/msm_gpu.c | 4 +-
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +-
7 files changed, 99 insertions(+), 55 deletions(-)
---
base-commit: f4ed0868966d96203fee6f2782508746ded2ce3f
change-id: 20230222-konrad-longbois-next-86d1a69532c2
Best regards,
--
Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>