Re: [PATCH RFC v8 10/56] x86/cpufeatures: Add SEV-SNP CPU feature

[Kalra, Ashish]

On 2/21/2023 3:21 PM, Sathyanarayanan Kuppuswamy wrote:
> On 2/20/23 10:38 AM, Michael Roth wrote:
> > From: Brijesh Singh <brijesh.singh@xxxxxxx>
> >
> > Add CPU feature detection for Secure Encrypted Virtualization with
> > Secure Nested Paging. This feature adds a strong memory integrity
> > protection to help prevent malicious hypervisor-based attacks like
> > data replay, memory re-mapping, and more.
> >
> > Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx>
> > Signed-off-by: Jarkko Sakkinen <jarkko@xxxxxxxxxxx>
> > Signed-off-by: Ashish Kalra <Ashish.Kalra@xxxxxxx>
>
> Too many signed-off-by's. Are you missing Co-developed-by?
>
> > Signed-off-by: Michael Roth <michael.roth@xxxxxxx>
> > ---
> >   arch/x86/include/asm/cpufeatures.h       | 1 +
> >   arch/x86/kernel/cpu/amd.c                | 5 +++--
> >   tools/arch/x86/include/asm/cpufeatures.h | 1 +
> >   3 files changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 1419c4e04d45..480b4eaef310 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -420,6 +420,7 @@
> >   #define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
> >   #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
> >   #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
> > +#define X86_FEATURE_SEV_SNP		(19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */
> >   #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
> >   #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
> >   
> > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> > index 860b60273df3..c7884198ad5b 100644
> > --- a/arch/x86/kernel/cpu/amd.c
> > +++ b/arch/x86/kernel/cpu/amd.c
> > @@ -558,8 +558,8 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
> >   	 *	      SME feature (set in scattered.c).
> >   	 *	      If the kernel has not enabled SME via any means then
> >   	 *	      don't advertise the SME feature.
> > -	 *   For SEV: If BIOS has not enabled SEV then don't advertise the
> > -	 *            SEV and SEV_ES feature (set in scattered.c).
>
> Did you remove the related scattered.c code mentioned above in a different patch?

That is part of the following commit:

commit fb35d30fe5b06cc24444f0405da8fbe0be5330d1
Author: Sean Christopherson <seanjc@xxxxxxxxxx>
Date:   Fri Jan 22 12:40:46 2021 -0800

    x86/cpufeatures: Assign dedicated feature word for 
CPUID_0x8000001F[EAX]

    Collect the scattered SME/SEV related feature flags into a dedicated
    word.  There are now five recognized features in CPUID.0x8000001F.EAX,
    with at least one more on the horizon (SEV-SNP).  Using a dedicated 
word
    allows KVM to use its automagic CPUID adjustment logic when reporting
    the set of supported features to userspace.

    No functional change intended.

    Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Reviewed-by: Brijesh Singh <brijesh.singh@xxxxxxx>
    Link: 
https://lkml.kernel.org/r/20210122204047.2860075-2-seanjc@xxxxxxxxxx

Thanks,
Ashish

> > +	 *   For SEV: If BIOS has not enabled SEV then don't advertise SEV and
> > +	 *	      any additional functionality based on it.
> >   	 *
> >   	 *   In all cases, since support for SME and SEV requires long mode,
> >   	 *   don't advertise the feature under CONFIG_X86_32.
> > @@ -594,6 +594,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
> >   clear_sev:
> >   		setup_clear_cpu_cap(X86_FEATURE_SEV);
> >   		setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
> > +		setup_clear_cpu_cap(X86_FEATURE_SEV_SNP);
> >   	}
> >   }
> >   
> > diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> > index b71f4f2ecdd5..e81606fcd2ab 100644
> > --- a/tools/arch/x86/include/asm/cpufeatures.h
> > +++ b/tools/arch/x86/include/asm/cpufeatures.h
> > @@ -417,6 +417,7 @@
> >   #define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
> >   #define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
> >   #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
> > +#define X86_FEATURE_SEV_SNP		(19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */
> >   #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
> >   #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
> >