Re: [PATCH V8 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

From: andy . shevchenko
Date: Mon Mar 06 2023 - 18:58:27 EST


Tue, Feb 14, 2023 at 10:01:13PM +0530, Devi Priya kirjoitti:
> Add pinctrl definitions for the TLMM of IPQ9574

...

> + depends on OF

No compile test on non-OF configurations?

> + depends on ARM64 || COMPILE_TEST

...

> +#define FUNCTION(fname) \

PINCTRL_PINFUNCTION() ?

> + [msm_mux_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }

...

> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \

Can you embed struct pingroup?

> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9 \
> + }, \
> + .nfuncs = 10, \
> + .ctl_reg = REG_SIZE * id, \
> + .io_reg = 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \
> + .intr_status_reg = 0xc + REG_SIZE * id, \
> + .intr_target_reg = 0x8 + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_target_bit = 5, \
> + .intr_target_kpss_val = 3, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }

...

> + PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta, prng_rosc2, gcc_plltest,
> + _, _),

Can be one line.

...

> +static const struct of_device_id ipq9574_pinctrl_of_match[] = {
> + { .compatible = "qcom,ipq9574-tlmm", },

> + { },

No comma for terminator line.

> +};

No MODULE_DEVICE_TABLE()?

--
With Best Regards,
Andy Shevchenko