Re: [PATCH v5 05/12] riscv: dts: starfive: jh7110: Add ethernet device nodes

[Guo Samin]

在 2023/3/5 6:57:18, Emil Renner Berthing 写道:
> On Fri, 3 Mar 2023 at 10:01, Samin Guo <samin.guo@xxxxxxxxxxxxxxxx> wrote:
>>
>> Add JH7110 ethernet device node to support gmac driver for the JH7110
>> RISC-V SoC.
>>
>> Signed-off-by: Yanhong Wang <yanhong.wang@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Samin Guo <samin.guo@xxxxxxxxxxxxxxxx>
>> ---
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 91 ++++++++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 09806418ed1b..2ce28292b721 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -233,6 +233,13 @@
>>                 #clock-cells = <0>;
>>         };
>>
>> +       stmmac_axi_setup: stmmac-axi-config {
>> +               snps,lpi_en;
>> +               snps,wr_osr_lmt = <4>;
>> +               snps,rd_osr_lmt = <4>;
>> +               snps,blen = <256 128 64 32 0 0 0>;
>> +       };
>> +
>>         tdm_ext: tdm-ext-clock {
>>                 compatible = "fixed-clock";
>>                 clock-output-names = "tdm_ext";
>> @@ -518,5 +525,89 @@
>>                         gpio-controller;
>>                         #gpio-cells = <2>;
>>                 };
>> +
>> +               gmac0: ethernet@16030000 {
>> +                       compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
>> +                       reg = <0x0 0x16030000 0x0 0x10000>;
>> +                       clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
>> +                                <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
>> +                                <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
>> +                       clock-names = "stmmaceth", "pclk", "ptp_ref",
>> +                                     "tx", "gtx";
>> +                       resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
>> +                                <&aoncrg JH7110_AONRST_GMAC0_AHB>;
>> +                       reset-names = "stmmaceth", "ahb";
>> +                       interrupts = <7>, <6>, <5>;
>> +                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
>> +                       phy-mode = "rgmii-id";
>> +                       snps,multicast-filter-bins = <64>;
>> +                       snps,perfect-filter-entries = <8>;
>> +                       rx-fifo-depth = <2048>;
>> +                       tx-fifo-depth = <2048>;
>> +                       snps,fixed-burst;
>> +                       snps,no-pbl-x8;
>> +                       snps,force_thresh_dma_mode;
>> +                       snps,axi-config = <&stmmac_axi_setup>;
>> +                       snps,tso;
>> +                       snps,en-tx-lpi-clockgating;
>> +                       snps,txpbl = <16>;
>> +                       snps,rxpbl = <16>;
>> +                       status = "disabled";
>> +                       phy-handle = <&phy0>;
>> +
>> +                       mdio {
>> +                               #address-cells = <1>;
>> +                               #size-cells = <0>;
>> +                               compatible = "snps,dwmac-mdio";
>> +
>> +                               phy0: ethernet-phy@0 {
>> +                                       reg = <0>;
>> +                               };
>> +                       };
>> +               };
>> +
>> +               gmac1: ethernet@16040000 {
>> +                       compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
>> +                       reg = <0x0 0x16040000 0x0 0x10000>;
>> +                       clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
>> +                                <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
>> +                       clock-names = "stmmaceth", "pclk", "ptp_ref",
>> +                                     "tx", "gtx";
>> +                       resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
>> +                                <&syscrg JH7110_SYSRST_GMAC1_AHB>;
>> +                       reset-names = "stmmaceth", "ahb";
>> +                       interrupts = <78>, <77>, <76>;
>> +                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
>> +                       phy-mode = "rgmii-id";
>> +                       snps,multicast-filter-bins = <64>;
>> +                       snps,perfect-filter-entries = <8>;
>> +                       rx-fifo-depth = <2048>;
>> +                       tx-fifo-depth = <2048>;
>> +                       snps,fixed-burst;
>> +                       snps,no-pbl-x8;
>> +                       snps,force_thresh_dma_mode;
>> +                       snps,axi-config = <&stmmac_axi_setup>;
>> +                       snps,tso;
>> +                       snps,en-tx-lpi-clockgating;
>> +                       snps,txpbl = <16>;
>> +                       snps,rxpbl = <16>;
>> +                       status = "disabled";
>> +                       phy-handle = <&phy1>;
>> +
>> +                       mdio {
>> +                               #address-cells = <1>;
>> +                               #size-cells = <0>;
>> +                               compatible = "snps,dwmac-mdio";
>> +
>> +                               phy1: ethernet-phy@1 {
>> +                                       reg = <0>;
> 
> I'm getting errors on eth1 unless this is set to <1>. In any case the
> number after @ in the node name should match the reg value.

Hi，Emil，which board are you using?  (v1.2a or v1.3b?). 
I have tested it on v1.2a and 1.3b, all network ports work normally when the phy address is set to 0.
Maybe your eth1 doesn't work for other reasons?

General, the phy address is fixed when the bord is designed.
(For example,the phy address of YT8512 depends on the hardware resistance pull-up or pull-down.
However, some phy addresses can be configured through software, but not yt8512.)

The phy address is a borad-related attribute, and I will follow Andrew's suggestion and put the phy address in borad*.dts


Best regards,
Samin
> 
>> +                               };
>> +                       };
>> +               };
>>         };
>>  };
>> --
>> 2.17.1
>>
>>
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-- 
Best regards,
Samin