Re: drivers/gpu/drm/bridge/fsl-ldb.c:101: possible loss of information.

[David Binderman]

Hello there Laurent,

>We could, but I don't think it will make any difference in practice as
>the maximum pixel clock frequency supported by the SoC is 80MHz (per
>LVDS channel). That would result in a 560MHz frequency returned by this
>function, well below the 31 bits limit.

Thanks for your explanation. I have a couple of suggestions for possible improvements:

1. Your explanatory text in a comment nearby. This helps all readers of the code.

2. Might the frequency go up to 300 MHz anytime soon ? The code will stop working then. 
In this case, I would suggest to put in a run time sanity check to make sure no 31 bit overflow. 

Just a couple of ideas for the code.

Regards

David Binderman