Re: [PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver

[Dmitry Rokosov]

On Thu, Mar 09, 2023 at 03:20:23PM +0100, Jerome Brunet wrote:
> 
> On Mon 06 Mar 2023 at 23:05, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote:
> 
> > On Mon, Mar 06, 2023 at 12:17:23PM +0100, Jerome Brunet wrote:
> >> 
> >> On Wed 01 Mar 2023 at 21:37, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote:
> >> 
> >> > Introduce PLL clock controller for Amlogic A1 SoC family.
> >> >
> >> > Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
> >> > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx>

[...]

> >> > +	},
> >> > +};
> >> > +
> >> > +static const struct pll_mult_range hifi_pll_mult_range = {
> >> > +	.min = 32,
> >> > +	.max = 64,
> >> > +};
> >> > +
> >> > +static const struct reg_sequence hifi_init_regs[] = {
> >> > +	{ .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
> >> > +	{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
> >> > +	{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 },
> >> > +	{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x00302000 },
> >> > +	{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18440 },
> >> 
> >> This last poke should not bits otherwise handled by parms.
> >> This is a rate init in disguise.
> >> 
> >
> > I believe, you are talking about hifi_pll clk_regmap conflicts with
> > hifi_init_regs. The above init sequence shouldn't affect pll regmap setup,
> > it doesn't touch them (we assume that default bit values are all zero):
> >
> >     .en = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >         .shift   = 28,
> >         .width   = 1,
> >     },
> >     // init_value = 0x01f18440
> >     // en_mask    = 0x10000000
> >
> >     .m = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >         .shift   = 0,
> >         .width   = 8,
> >     },
> >     // init_value = 0x01f18440
> >     // m_mask     = 0x0000000f
> 
> mask is 0xff with width 8
> 

Ah, you're right. Anyway, I think this is just init value and it's okay
to set it during initialization and rewrite after in parameter
propagation stage.

> >
> >     .n = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >         .shift   = 10,
> >         .width   = 5,
> >     },
> >     // init_value = 0x01f18440
> >     // n_mask     = 0x00007c00
> >                            ^
> >                     oops, one overlap
> >                     but why we can't set init value for pre_sel?
> >
> >     .frac = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL1,
> >         .shift   = 0,
> >         .width   = 19,
> >     },
> >     // init_value = 0x01800000
> >     // frac_mask  = 0x0007ffff
> >
> >     .current_en = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >         .shift   = 26,
> >         .width   = 1,
> >     },
> >     // init_value      = 0x01f18440
> >     // current_en_mask = 0x04000000
> >
> >     .l_detect = {
> >         .reg_off = ANACTRL_HIFIPLL_CTRL2,
> >         .shift   = 6,
> >         .width   = 1,
> >     },
> >     // init_value    = 0x00001100
> >     // l_detect_mask = 0x00000040
> >
> >> > +};
> >> > +
> >> > +static struct clk_regmap hifi_pll = {
> >> > +	.data = &(struct meson_clk_pll_data){
> >> > +		.en = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> > +			.shift   = 28,
> >> > +			.width   = 1,
> >> > +		},
> >> > +		.m = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> > +			.shift   = 0,
> >> > +			.width   = 8,
> >> > +		},
> >> > +		.n = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> > +			.shift   = 10,
> >> > +			.width   = 5,
> >> > +		},
> >> > +		.frac = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_CTRL1,
> >> > +			.shift   = 0,
> >> > +			.width   = 19,
> >> > +		},
> >> > +		.l = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_STS,
> >> > +			.shift   = 31,
> >> > +			.width   = 1,
> >> > +		},
> >> > +		.current_en = {
> >> > +			.reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> > +			.shift   = 26,
> >> > +			.width   = 1,
> >> > +		},
> >> > +		.l_detect = {
> >> 
> >> What is this ?
> >> 
> >
> > Lock detection module.
> >
> > This is IP module included to new PLL power-on sequence. From clk-pll.c
> > patchset:
> >
> > /*
> >  * Compared with the previous SoCs, self-adaption current module
> >  * is newly added for A1, keep the new power-on sequence to enable the
> >  * PLL. The sequence is:
> >  * 1. enable the pll, delay for 10us
> >  * 2. enable the pll self-adaption current module, delay for 40us
> >  * 3. enable the lock detect module
> >  */
> 
> Ok. I missed this is the PLL driver
> 

No problem.

[...]

-- 
Thank you,
Dmitry