[PATCH v2 0/2] Add device-tree support for CPSW9G on J721E SoC

[Siddharth Vadapalli]

Hello,

This series adds the device-tree nodes for CPSW9G instance of CPSW
Ethernet Switch on TI's J721E SoC. Additionally, an overlay file is also
added to enable CPSW9G nodes in QSGMII mode with the Add-On J7 QUAD Port
Ethernet expansion QSGMII daughtercard.

---
Changes from v1:
1. Rename node name "mdio_pins_default" to "mdio0-pins-default", since
   node names shouldn't contain underscores.
2. Change node label "mdio_pins_default" to "mdio0_pins_default".

The reason for adding 0 after mdio with the above changes, is to indicate
the association of the cpsw0 instance of CPSW with this instance of MDIO.

v1:
https://lore.kernel.org/r/20230310092804.692303-1-s-vadapalli@xxxxxx

Siddharth Vadapalli (2):
  arm64: dts: ti: k3-j721e: Add CPSW9G nodes
  arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII
    mode

 arch/arm64/boot/dts/ti/Makefile               |   4 +
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 107 +++++++++++++
 .../dts/ti/k3-j721e-quad-port-eth-exp.dtso    | 148 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e.dtsi          |   1 +
 4 files changed, 260 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso

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2.25.1