Re: [PATCH 1/7] irqchip/gic-v3: Add a DMA Non-Coherent flag

[Marc Zyngier]

On Fri, 10 Mar 2023 09:53:16 +0000,
Lucas Tanure <lucas.tanure@xxxxxxxxxxxxx> wrote:
> 
> On 10-03-2023 08:56, Marc Zyngier wrote:
> > On 2023-03-10 08:05, Lucas Tanure wrote:
> >> The GIC600 integration in RK356x, used in rk3588, doesn't support
> >> any of the shareability or cacheability attributes, and requires
> >> both values to be set to 0b00 for all the ITS and Redistributor
> >> tables.
> >> 
> >> This is loosely based on prior work from XiaoDong Huang and
> >> Peter Geis fixing this issue specifically for Rockchip 356x.
> > 
> > No.
> > 
> > If we are going to do *anything* about this thing, it is by
> > describing the actual topology.
> What do you mean by describe the topology?

Exactly what it means. Describe which shareability domains the GIC is
in w.r.t the whole SoC. Do it consistently over the whole SoC.

	M.

-- 
Without deviation from the norm, progress is not possible.