Re: [PATCH v4 3/3] dt-bindings: gpio: add NPCM sgpio driver bindings

[Krzysztof Kozlowski]

On 13/03/2023 11:38, Jim Liu wrote:
> Hi Krzysztof
> 
> Sorry for the mistake.
> I think I need to explain more details about the clock.

It's still top-posting.

> 
> The NPCM7xx / NPCM8xx  SGPIO feature have 4 pins.
> picture is as below:
> https://drive.google.com/file/d/1E9i_Avh-AZV9IEZO1HLMT4EtgCBe46OV/view?usp=sharing
> 
> The clock is generated from npcm7xx APB.
> The bus frequency is derived from npcm7xx APB not HC595/HC165.
> Users can connect  1~8 HC595 on DOUT pin to decode the serial data for
> HC595 A~H pin
> and can connect  1~8 HC165 on DIN pin to encode the serial data to
> send to NPCM7xx.
> 
> The test device is as below:
> https://pdf1.alldatasheet.com/datasheet-pdf/view/345467/TI/SN74HC595N.html
> https://pdf1.alldatasheet.com/datasheet-pdf/view/27899/TI/SN74HC165N.html
> 
> NPCM7xx/NPCM8xx have two sgpio modules;
> each module can support up to 64 output pins,and up to 64 input pins.
> If the user needs 64 output pins , user needs to connect 8 HC595.
> If the user needs 64 input pins , user needs to connect 8 HC165.
> 
> the HC595 and HC165 connect is as below:
> NPCM7xx_DOUT    ->   HC595  SER pin
> NPCM7xx_SCLK     ->   HC595  SRCLK pin
> NPCM7xx_LDSH    ->    HC595  RCLK pin
> 
> NPCM7xx_SCLK     ->   HC165  CLK pin
> NPCM7xx_LDSH     ->   HC165  SH/LD pin
> NPCM7xx_DIN        ->    HC165  QH pin
> 
> The frequency is not derived from the input clock. so i think maybe
> the yaml needs to describe it.

That's not what your code was saying. It said:
"Directly connected to APB bus and its shift clock is from APB bus clock
divided by a programmable value."

> if yaml file still didn't need please let me know.

Now read the description of bus-frequency:
"Legacy property for fixed bus frequencies"

Don't add legacy properties to new bindings. You have
assigned-clock-rates and clocks properties.

Best regards,
Krzysztof