[Patch v4 07/10] arm64: tegra: Add cpu OPP tables and interconnects property

From: Sumit Gupta
Date: Mon Mar 27 2023 - 12:17:09 EST

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Previous message: Sumit Gupta: "[Patch v4 06/10] dt-bindings: tegra: add icc ids for dummy MC clients"
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Add OPP table and interconnects property to scale DDR frequency with
CPU frequency for better performance. Each operating point entry of
the OPP table has CPU freq to per MC channel bandwidth mapping.
One table is added for each cluster even though the table data is
same because the bandwidth request is per cluster. This is done
because OPP framework creates a single icc path and hence single
bandwidth request if the table is marked as 'opp-shared' and shared
among all clusters. For us, the OPP table data is same but the MC
Client ID argument to interconnects property is different for each
cluster. So, having per cluster table makes different icc path for
each cluster and helps to make per cluster BW requests.

Signed-off-by: Sumit Gupta <sumitg@xxxxxxxxxx>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 276 +++++++++++++++++++++++
1 file changed, 276 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 348113b4928a..6f4aa1a93688 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -3013,6 +3013,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl0_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3029,6 +3032,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl0_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3045,6 +3051,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl0_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3061,6 +3070,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl0_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3077,6 +3089,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl1_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3093,6 +3108,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl1_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3109,6 +3127,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl1_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3125,6 +3146,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl1_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3141,6 +3165,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl2_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3157,6 +3184,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl2_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3173,6 +3203,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl2_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3189,6 +3222,9 @@

enable-method = "psci";

+ operating-points-v2 = <&cl2_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
+
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -3445,4 +3481,244 @@
interrupt-parent = <&gic>;
always-on;
};
+
+ cl0_opp_tbl: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cl0_ch1_opp1: opp-115200000 {
+ opp-hz = /bits/ 64 <115200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp2: opp-268800000 {
+ opp-hz = /bits/ 64 <268800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp3: opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp5: opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp6: opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp7: opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp8: opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl0_ch1_opp9: opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl0_ch1_opp10: opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl0_ch1_opp11: opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl0_ch1_opp12: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl0_ch1_opp13: opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ cl0_ch1_opp14: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6400000>;
+ };
+
+ cl0_ch1_opp15: opp-2201600000 {
+ opp-hz = /bits/ 64 <2201600000>;
+ opp-peak-kBps = <6400000>;
+ };
+ };
+
+ cl1_opp_tbl: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cl1_ch1_opp1: opp-115200000 {
+ opp-hz = /bits/ 64 <115200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp2: opp-268800000 {
+ opp-hz = /bits/ 64 <268800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp3: opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp5: opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp6: opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp7: opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp8: opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl1_ch1_opp9: opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl1_ch1_opp10: opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl1_ch1_opp11: opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl1_ch1_opp12: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl1_ch1_opp13: opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ cl1_ch1_opp14: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6400000>;
+ };
+
+ cl1_ch1_opp15: opp-2201600000 {
+ opp-hz = /bits/ 64 <2201600000>;
+ opp-peak-kBps = <6400000>;
+ };
+ };
+
+ cl2_opp_tbl: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cl2_ch1_opp1: opp-115200000 {
+ opp-hz = /bits/ 64 <115200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp2: opp-268800000 {
+ opp-hz = /bits/ 64 <268800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp3: opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp4: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp5: opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp6: opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp7: opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp8: opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ cl2_ch1_opp9: opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl2_ch1_opp10: opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <1632000>;
+ };
+
+ cl2_ch1_opp11: opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl2_ch1_opp12: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <2660000>;
+ };
+
+ cl2_ch1_opp13: opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ cl2_ch1_opp14: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6400000>;
+ };
+
+ cl2_ch1_opp15: opp-2201600000 {
+ opp-hz = /bits/ 64 <2201600000>;
+ opp-peak-kBps = <6400000>;
+ };
+ };
};
--
2.17.1

Next message: Javier Martinez Canillas: "Re: [PATCH v2] arm64: dts: rk3399-pinephone-pro: Add internal display support"
Previous message: Sumit Gupta: "[Patch v4 06/10] dt-bindings: tegra: add icc ids for dummy MC clients"
In reply to: Sumit Gupta: "[Patch v4 06/10] dt-bindings: tegra: add icc ids for dummy MC clients"
Next in thread: Sumit Gupta: "[Patch v4 08/10] cpufreq: tegra194: add OPP support and set bandwidth"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]