[PATCH V2 6/6] arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema
From: Peng Fan (OSS)
Date: Mon Mar 27 2023 - 23:32:55 EST
From: Peng Fan <peng.fan@xxxxxxx>
The dtschema requires 'grp' in the end, so update the name
Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
index 9fbbbb556c0b..1eb1fe7ebde8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
@@ -264,7 +264,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -280,7 +280,7 @@ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
--
2.37.1