Re: [PATCH v1 3/3] riscv: dts: starfive: add tdm node and sound card

[Conor Dooley]

On Thu, Mar 30, 2023 at 09:43:10AM +0200, Krzysztof Kozlowski wrote:
> On 29/03/2023 17:33, Walker Chen wrote:
> > Add the tdm controller node and sound card for the StarFive JH7110 SoC.

> > +		compatible = "fixed-clock";
> > +		clock-output-names = "wm8960_mclk";
> > +		#clock-cells = <0>;
> > +	};
> > +
> >  	i2srx_bclk_ext: i2srx-bclk-ext-clock {
> >  		compatible = "fixed-clock";
> >  		clock-output-names = "i2srx_bclk_ext";
> > @@ -375,6 +381,27 @@
> >  			status = "disabled";
> >  		};
> >  
> > +		tdm: tdm@10090000 {
> > +			compatible = "starfive,jh7110-tdm";
> > +			reg = <0x0 0x10090000 0x0 0x1000>;
> > +			clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
> > +				 <&syscrg JH7110_SYSCLK_TDM_APB>,
> > +				 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
> > +				 <&syscrg JH7110_SYSCLK_TDM_TDM>,
> > +				 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> > +				 <&tdm_ext>;
> > +			clock-names = "tdm_ahb", "tdm_apb",
> > +				      "tdm_internal", "tdm",
> > +				      "mclk_inner", "tdm_ext";
> > +			resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
> > +				 <&syscrg JH7110_SYSRST_TDM_APB>,
> > +				 <&syscrg JH7110_SYSRST_TDM_CORE>;
> > +			dmas = <&dma 20>, <&dma 21>;
> > +			dma-names = "rx","tx";
> > +			#sound-dai-cells = <0>;
> > +			status = "disabled";
> > +		};
> > +
> >  		stgcrg: clock-controller@10230000 {
> >  			compatible = "starfive,jh7110-stgcrg";
> >  			reg = <0x0 0x10230000 0x0 0x10000>;
> > @@ -601,5 +628,12 @@
> >  			#reset-cells = <1>;
> >  			power-domains = <&pwrc JH7110_PD_VOUT>;
> >  		};
> > +
> > +		sound0: snd-card0 {
> 
> 1. Why card0?
> 2. Where is this node located? In MMIO bus? Run some basic checks on
> your DTS before submitting upstream.
> dtbs_check
> dtbs W=1
> 
> 3. Why this is even in the DTSI? This really looks wrong.

Excuse me for not following here, but Walker, could you point me at
where in the schematic for the VisionFive 2 that this wm8960 actually
is?
I know ~nothing about audio, but good old Google tells me that this is a
dedicated codec chip and I was looking at [1] and could not easily find
it on the schematic.

Thanks,
Conor.

1 https://doc-en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf

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