Re: [PATCH] perf/x86/intel: Define bit macros for FixCntrCtl MSR

[Peter Zijlstra]

On Thu, Mar 30, 2023 at 09:28:46AM +0800, Dapeng Mi wrote:
> Define bit macros for FixCntrCtl MSR and replace the bit hardcoding
> with these bit macros. This would make code be more human-readable.
> 
> Perf commands 'perf stat -e "instructions,cycles,ref-cycles"' and
> 'perf record -e "instructions,cycles,ref-cycles"' pass.
> 
> Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/events/intel/core.c      | 18 +++++++++---------
>  arch/x86/include/asm/perf_event.h | 10 ++++++++++
>  2 files changed, 19 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 070cc4ef2672..b7c0bb78ed59 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2451,7 +2451,7 @@ static void intel_pmu_disable_fixed(struct perf_event *event)
>  
>  	intel_clear_masks(event, idx);
>  
> -	mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
> +	mask = intel_fixed_bits(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
>  	cpuc->fixed_ctrl_val &= ~mask;

So maybe it's me, but I find the original far easier to read :/ That new
things I need to look up every single identifier before I can tell wth
it does.