Re: [PATCH 3/3] spi: s3c64xx: support interrupt based pio mode

[Mark Brown]

On Tue, Apr 04, 2023 at 03:00:11PM +0900, Jaewon Kim wrote:

> This patch adds IRQ based PIO mode instead of cpu polling.
> By using the FIFO trigger level, interrupts are received.
> CPU consumption is reduced in PIO mode because registers are not
> constantly checked.

Is there some lower limit where it's still worth using polling, for
example for just one or two bytes like a register address?  Taking an
interrupt isn't free...

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