[PATCH 0/4] Manage register access to control delay during sec update

[Ilpo Järvinen]

Manage handshake register access on Max 10 FPGA cards that have a major
slowdown on reading handshake registers during secure update prepare and
write phases. The problem does not occur with PMCI-based cards.

Ilpo Järvinen (4):
  mfd: intel-m10-bmc: Move core symbols to own namespace
  mfd: intel-m10-bmc: Create m10bmc_sys_update_bits()
  mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header
  mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers

 drivers/fpga/intel-m10-bmc-sec-update.c | 47 ++++++++------
 drivers/hwmon/intel-m10-bmc-hwmon.c     |  1 +
 drivers/mfd/intel-m10-bmc-core.c        | 84 ++++++++++++++++++++++++-
 drivers/mfd/intel-m10-bmc-pmci.c        |  5 ++
 drivers/mfd/intel-m10-bmc-spi.c         | 15 +++++
 include/linux/mfd/intel-m10-bmc.h       | 42 +++++++++----
 6 files changed, 161 insertions(+), 33 deletions(-)

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2.30.2