On Mon, Mar 27, 2023 at 01:59:51PM +0200, Pierre Gondois wrote:
The cache information can be extracted from either a Device
Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1
for arm64).
The clidr_el1 register is used only if DT/ACPI information is not
available. It does not states how caches are shared among CPUs.
Add a use_arch_cache_info field/function to identify when the
DT/ACPI doesn't provide cache information. Use this information
to assume L1 caches are privates and L2 and higher are shared among
all CPUs.
Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx>
---
arch/arm64/kernel/cacheinfo.c | 5 +++++
drivers/base/cacheinfo.c | 20 ++++++++++++++++++--
include/linux/cacheinfo.h | 2 ++
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index c307f69e9b55..b6306cda0fa7 100644
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -96,3 +96,8 @@ int populate_cache_leaves(unsigned int cpu)
}
return 0;
}
+
+bool use_arch_cache_info(unsigned int cpu)
+{
+ return true;
+}
It would be a lot nicer if this was a static inline function in a header
rather than a weak symbol.
Will