Re: [PATCH v2 0/5] Parse the PCIe AER and set to relevant registers

[Bjorn Helgaas]

[+cc Sathy, Ming, since they commented on the previous version]

On Tue, Nov 15, 2022 at 11:11:15AM +0800, LeoLiu-oc wrote:
> From: leoliu-oc <leoliu-oc@xxxxxxxxxxx>
> 
> According to the sec 18.3.2.4, 18.3.2.5 and 18.3.2.6 in ACPI r6.5, the
> register values form HEST PCI Express AER Structure should be written to
> relevant PCIe Device's AER Capabilities. So the purpose of the patch set
> is to extract register values from HEST PCI Express AER structures and
> program them into AER Capabilities. Refer to the ACPI Spec r6.5 for a more
> detailed description.

I wasn't involved in this part of the ACPI spec, and I don't
understand how this is intended to work.

I see that this series extracts AER mask, severity, and control
information from the ACPI HEST table and uses it to configure PCIe
devices as they are enumerated.

What I don't understand is how this relates to ownership of the AER
capability as negotiated by the _OSC method.  Firmware can configure
the AER capability itself, and if it retains control of the AER
capability, the OS can't write to it (with the exception of clearing
EDR error status), so this wouldn't be necessary.

If the OS owns the AER capability, I assume it gets to decide for
itself how to configure AER, no matter what the ACPI HEST says.

Maybe this is intended for the case where firmware retains AER
ownership but the OS uses native hotplug (pciehp), and this is a way
for the OS to configure new devices as the firmware expects?  But in
that case, we still have the problem that the OS can't write to the
AER capability to do this configuration.

Bjorn