Re: [PATCH 3/5] clk: imx: imx8ulp: keep MU0_B clock enabled always

[Abel Vesa]

On 23-03-31 14:38:12, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@xxxxxxx>
> 
> Keep the A35<->M33 MU0_B clock enabled always for low power
> communication.
> 
> Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
> Signed-off-by: Jacky Bai <ping.bai@xxxxxxx>
> Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
> ---

Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>

>  drivers/clk/imx/clk-imx8ulp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c
> index 3cf4b094dfff..0dd48e8159ee 100644
> --- a/drivers/clk/imx/clk-imx8ulp.c
> +++ b/drivers/clk/imx/clk-imx8ulp.c
> @@ -376,7 +376,7 @@ static int imx8ulp_clk_pcc3_init(struct platform_device *pdev)
>  	clks[IMX8ULP_CLK_DMA1_CH29] = imx_clk_hw_gate("pcc_dma1_ch29", "xbar_ad_divplat", base + 0x7c, 30);
>  	clks[IMX8ULP_CLK_DMA1_CH30] = imx_clk_hw_gate("pcc_dma1_ch30", "xbar_ad_divplat", base + 0x80, 30);
>  	clks[IMX8ULP_CLK_DMA1_CH31] = imx_clk_hw_gate("pcc_dma1_ch31", "xbar_ad_divplat", base + 0x84, 30);
> -	clks[IMX8ULP_CLK_MU0_B] = imx_clk_hw_gate("mu0_b", "xbar_ad_divplat", base + 0x88, 30);
> +	clks[IMX8ULP_CLK_MU0_B] = imx_clk_hw_gate_flags("mu0_b", "xbar_ad_divplat", base + 0x88, 30, CLK_IS_CRITICAL);
>  	clks[IMX8ULP_CLK_MU3_A] = imx_clk_hw_gate("mu3_a", "xbar_ad_divplat", base + 0x8c, 30);
>  
>  	imx_check_clk_hws(clks, clk_data->num);
> -- 
> 2.37.1
>