Re: [PATCH v5 1/2] spi: dw: Add 32 bpw support to DW DMA Controller

[Serge Semin]

On Tue, Apr 11, 2023 at 03:13:49PM +0300, Andy Shevchenko wrote:
> On Thu, Mar 30, 2023 at 06:34:49AM +0000, Joy Chakraborty wrote:
> 
> First of all the Subject is wrong. You are not touching DMA controller.
> Needs to be rephrased.
> 
> > Add Support for AxSize = 4 bytes configuration from dw dma driver if
> 
> SPI DMA driver
> 
> (or something like this, note capital letters for acronyms).
> 
> > n_bytes i.e. number of bytes per write to fifo is 3 or 4.
> > 
> > Number of bytes written to fifo per write is depended on the bits/word
> > configuration being used which the DW core driver translates to n_bytes.
> 
> ...
> 
> >  static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
> >  {
> > -	if (n_bytes == 1)
> > +	switch (n_bytes) {
> > +	case 1:
> >  		return DMA_SLAVE_BUSWIDTH_1_BYTE;
> > -	else if (n_bytes == 2)
> > +	case 2:
> >  		return DMA_SLAVE_BUSWIDTH_2_BYTES;
> > -
> > -	return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> 
> > +	case 3:
> 
> I'm not sure about this.

This actually makes sense seeing the function argument can have values
1, 2, _3_ and 4:
dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
transfer->bits_per_word = __F__(master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32));
...
dw_spi_dma_convert_width(dws->n_bytes)

The spi_transfer.bits_per_word field value depends on the
SPI peripheral device communication protocol requirements which may
imply the 3-bytes word xfers (even though it's indeed unluckily).

This semantic will also match to what we currently have in the
IRQ-based SPI-transfer implementation (see dw_writer() and
dw_reader()).

-Serge(y)

> 
> > +	case 4:
> > +		return DMA_SLAVE_BUSWIDTH_4_BYTES;
> > +	default:
> > +		return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> > +	}
> >  }
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
>