Re: [PATCH v5 2/2] spi: dw: Add dma controller capability checks

[Andy Shevchenko]

On Tue, Apr 11, 2023 at 05:37:58PM +0300, Serge Semin wrote:
> On Tue, Apr 11, 2023 at 03:18:34PM +0300, Andy Shevchenko wrote:
> > On Thu, Mar 30, 2023 at 06:34:50AM +0000, Joy Chakraborty wrote:

...

> > > +	if (!(tx.directions & BIT(DMA_MEM_TO_DEV) &&
> > > +	      rx.directions & BIT(DMA_DEV_TO_MEM)))
> > > +		return -ENXIO;
> > 
> 
> > What about simplex transfers where we only care about sending or receiving data
> > and using dummy data for the other channel? Doesn't this make a regression for
> > that types of transfers? (Or, if we don't support such, this should be explained
> > in the commit message at least.)
> 
> I don't think the code above is that much relevant for the half-duplex
> transfers. The DW APB SSI-DMA driver requires both Tx and Rx channels
> being specified thus supporting the Full-duplex transfers at least in
> case of the TxRx and Rx-only SPI-transfers (the later case relies on
> having the dummy buffers supplied by the SPI-core). Thus the channels
> must support the corresponding DMA-directions.
> 
> Indeed the Tx-only DMA-based SPI-transfers implementation in the
> driver implies not using the Rx DMA-channel, but even in that case the
> Rx-channel still needs to be specified otherwise the DW APB SSI-DMA
> setup methods will halt with error returned. So unless there are cases
> with dummy Rx DMA-channels (which I very much doubt there is) I don't
> see the suggested update causing a regression. Am I missing something?

Okay, so since it's not a problem, can we explain this in the commit message
then? A summary of the above, perhaps?

...

> Do you still think otherwise?

Answered above.

-- 
With Best Regards,
Andy Shevchenko