Re: [PATCH v4] PCI: Fix up L1SS capability for Intel Apollo Lake Root Port

[Bjorn Helgaas]

On Wed, Apr 12, 2023 at 12:02:13AM +0800, Ron Lee wrote:
> On Google Coral and Reef family Chromebooks with Intel Apollo Lake
> SoC, firmware clobbers the header of the L1 PM Substates capability and
> the previous capability when returning D3cold to D0.
> 
> Save those header at enumeration-time and restore them at resume.
> 
> Link: https://lore.kernel.org/linux-pci/CAFJ_xbq0cxcH-cgpXLU4Mjk30+muWyWm1aUZGK7iG53yaLBaQg@xxxxxxxxxxxxxx/T/#u
> Signed-off-by: Ron Lee <ron.lee@xxxxxxxxx>

Applied to pci/aspm for v6.4, thanks!

> ---
> Changes from v3: 
> - Move to arch/x86/pci/fixup.c
> - Save prev cap offset & header, L1SS offset & header at enumeration-time
>   and restore them at resume
> - Remove CONFIG_PCIEASPM directive
> - Stop traversal if L1SS capability was found
> 
>  arch/x86/pci/fixup.c | 59 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index 615a76d70019..28335aaa6c33 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c
> @@ -824,3 +824,62 @@ static void rs690_fix_64bit_dma(struct pci_dev *pdev)
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
>  
>  #endif
> +
> +/*
> + * When returning from D3cold to D0, firmware on some Google Coral and Reef
> + * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of
> + * both the L1 PM Substates capability and the previous capability for the
> + * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1".
> + *
> + * Save those values at enumeration-time and restore them at resume.
> + */
> +
> +static u16 prev_cap, l1ss_cap;
> +static u32 prev_header, l1ss_header;
> +
> +static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev)
> +{
> +	int pos = PCI_CFG_SPACE_SIZE, prev = 0;
> +	u32 header, pheader = 0;
> +
> +	while (pos) {
> +		pci_read_config_dword(dev, pos, &header);
> +		if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS) {
> +			prev_cap = prev;
> +			prev_header = pheader;
> +			l1ss_cap = pos;
> +			l1ss_header = header;
> +			return;
> +		}
> +
> +		prev = pos;
> +		pheader = header;
> +		pos = PCI_EXT_CAP_NEXT(header);
> +	}
> +}
> +
> +static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
> +{
> +	u32 header;
> +
> +	if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header)
> +		return;
> +
> +	/* Fixup the header of L1SS Capability if missing */
> +	pci_read_config_dword(dev, l1ss_cap, &header);
> +	if (header != l1ss_header) {
> +		pci_write_config_dword(dev, l1ss_cap, l1ss_header);
> +		pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
> +			 header, l1ss_header);
> +	}
> +
> +	/* Fixup the link to L1SS Capability if missing */
> +	pci_read_config_dword(dev, prev_cap, &header);
> +	if (header != prev_header) {
> +		pci_write_config_dword(dev, prev_cap, prev_header);
> +		pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
> +			 header, prev_header);
> +	}
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
> +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
> -- 
> 2.17.1
>