Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core

[Conor Dooley]

On Thu, Apr 13, 2023 at 07:26:02PM +0100, Lad, Prabhakar wrote:

> > The simplest solution may to just be making the erratum depend on 64BIT?
> >
> I dont think this will work, as pmem.c is compiled unconditionally.

That'll teach me to write things like this first thing in the morning.
I somehow got it in my head that the alternative would be removed by the
preprocessor if it was not enabled. After testing it, that's not what
happened.
My excuse is being tired from the gym and insufficiently caffeinated,
sorry!

> Is
> dma-noncoherent.c also valid for RISCV-32? If not then we can make
> pmem.c compile conditionally if DMA non-coherenet is enabled and we
> make DMA non-coherent depend on 64bit.

Could you drop the {s,l}d in exchange for {s,l}w instead, or am I
progressing even further into braino territory?

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