Re: [PATCH v3 2/4] cacheinfo: Check cache properties are present in DT

[Pierre Gondois]

Hello Florian,

On 4/13/23 20:16, Florian Fainelli wrote:
> On 4/13/23 02:14, Pierre Gondois wrote:
> > If a Device Tree (DT) is used, the presence of cache properties is
> > assumed. Not finding any is not considered. For arm64 platforms,
> > cache information can be fetched from the clidr_el1 register.
> > Checking whether cache information is available in the DT
> > allows to switch to using clidr_el1.
> >
> > init_of_cache_level()
> > \-of_count_cache_leaves()
> > will assume there a 2 cache leaves (L1 data/instruction caches), which
> > can be different from clidr_el1 information.
> >
> > cache_setup_of_node() tries to read cache properties in the DT.
> > If there are none, this is considered a success. Knowing no
> > information was available would allow to switch to using clidr_el1.
> >
> > Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves")
> > Reported-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> > Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/
> > Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx>
>
> Humm, it would appear that the cache levels and topology is still
> provided, despite the lack of cache properties in the Device Tree which
> is intended by this patch set however we lost the size/ways/sets
> information, could we not complement the missing properties here?
>
> If this is out of the scope of what you are doing:
>
> Tested-by: Florian Fainelli <f.fainelli@xxxxxxxxx>

I submitted a v4 at:
https://lore.kernel.org/all/20230414081453.244787-1-pierre.gondois@xxxxxxx/

I haven't included your Tested-by as there were some small changes.
If you consider these changes are small enough to include your tag,
please let know,

Regards,
Pierre