Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core

[Lad, Prabhakar]

On Thu, Apr 13, 2023 at 10:06 PM Lad, Prabhakar
<prabhakar.csengg@xxxxxxxxx> wrote:
>
> On Thu, Apr 13, 2023 at 7:46 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
> >
> > > Is
> > > dma-noncoherent.c also valid for RISCV-32? If not then we can make
> > > pmem.c compile conditionally if DMA non-coherenet is enabled and we
> > > make DMA non-coherent depend on 64bit.
> >
> > Could you drop the {s,l}d in exchange for {s,l}w instead, or am I
> > progressing even further into braino territory?
> Just the direct exchange wont work in addition shifting + oring to
> take care of 64-bit will require. (Correct me if I'm wrong here)
>
> I was wondering now if we need to store/restore the s0 and ra
> registers. I stumbled on an X86 implementation which has call [0] in
> the ALTERNATIVE_X() macro but here we dont store/restore the
> registers. Is the RISC-V implementation of ALT macro different
> compared to x86?
>
I did try a call without stroe/restore of s0 and ra registers and that
didn't work!. So I have re-written the assembly code which makes
32-bit RISC-V compilers happy. Once done with the testing I'll send a
new version of this series. Hopefully the last ;)

Cheers,
Prabhakar