Re: [PATCH v3 4/5] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node

[Krzysztof Kozlowski]

On 19/04/2023 08:17, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@xxxxxx>
> 
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
> 
> Signed-off-by: Rahul T R <r-ravikumar@xxxxxx>
> [j-choudhary@xxxxxx: move all k3-j784s4-main.dtsi changes together]
> Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 77 ++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 51aa476dedba..739741e93bc1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1373,4 +1373,81 @@ main_spi7: spi@2170000 {
>  		clocks = <&k3_clks 383 1>;
>  		status = "disabled";
>  	};
> +
> +	mhdp: dp-bridge@a000000 {
> +		compatible = "ti,j721e-mhdp8546";
> +
> +		reg = <0x0 0xa000000 0x0 0x30a00>,
> +		      <0x0 0x4f40000 0x0 0x20>;
> +		reg-names = "mhdptx", "j721e-intg";
> +
> +		clocks = <&k3_clks 217 11>;
> +
> +		interrupt-parent = <&gic500>;
> +		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> +
> +		status = "disabled";
> +
> +		dp0_ports: ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	dss: dss@4a00000 {
> +		compatible = "ti,j721e-dss";
> +		reg =
> +			<0x00 0x04a00000 0x00 0x10000>,

Fix indent/stray line break.

> +			<0x00 0x04a10000 0x00 0x10000>,
> +			<0x00 0x04b00000 0x00 0x10000>,
> +			<0x00 0x04b10000 0x00 0x10000>,
> +
> +			<0x00 0x04a20000 0x00 0x10000>,
> +			<0x00 0x04a30000 0x00 0x10000>,
> +			<0x00 0x04a50000 0x00 0x10000>,
> +			<0x00 0x04a60000 0x00 0x10000>,
> +
> +			<0x00 0x04a70000 0x00 0x10000>,
> +			<0x00 0x04a90000 0x00 0x10000>,
> +			<0x00 0x04ab0000 0x00 0x10000>,
> +			<0x00 0x04ad0000 0x00 0x10000>,
> +
> +			<0x00 0x04a80000 0x00 0x10000>,
> +			<0x00 0x04aa0000 0x00 0x10000>,
> +			<0x00 0x04ac0000 0x00 0x10000>,
> +			<0x00 0x04ae0000 0x00 0x10000>,
> +			<0x00 0x04af0000 0x00 0x10000>;
> +
> +		reg-names = "common_m", "common_s0",
> +			"common_s1", "common_s2",
> +			"vidl1", "vidl2","vid1","vid2",
> +			"ovr1", "ovr2", "ovr3", "ovr4",
> +			"vp1", "vp2", "vp3", "vp4",
> +			"wb";
> +
> +		clocks =	<&k3_clks 218 0>,

Broken indentation.



Best regards,
Krzysztof