Re: SMP enablement on Cortex-R52 (using PSCI ?)

[Sudeep Holla]

On Wed, Apr 19, 2023 at 06:50:26PM +0100, Robin Murphy wrote:
> On 19/04/2023 9:47 am, Sudeep Holla wrote:
> > 
> > I will check with the authors if EL3 is a must for PSCI implementation, but
> > IMO it must not be though every aspects described in the spec may not apply
> > when used across EL2/EL1 boundaries especially when EL3 is not implemented
> > in the hardware.
> 
> Xen could provide PSCI to EL1 guests using the HVC conduit. However if EL2
> is the highest implemented EL, then Xen is the most privileged software in
> the system - it would have to own the EL2 exception vectors, and it would
> have to own the low-level CPU bringup code. At that point it just wouldn't
> make much sense to HVC *itself* via the PSCI protocol when it could simply
> call the function directly.
>

Agreed, I was focussing to much just on EL2/EL1. I don't know details on how
power management responsibilities are split between Dom0 and hypervisor, but
I am more interested in understanding how cpuidle/suspend would be structured
with the direct function calls.

-- 
Regards,
Sudeep