RE: [PATCH v6 4/5] perf: CXL Performance Monitoring Unit driver

[Dan Williams]

Jonathan Cameron wrote:
> CXL rev 3.0 introduces a standard performance monitoring hardware
> block to CXL. Instances are discovered using CXL Register Locator DVSEC
> entries. Each CXL component may have multiple PMUs.
> 
> This initial driver supports a subset of types of counter.
> It supports counters that are either fixed or configurable, but requires
> that they support the ability to freeze and write value whilst frozen.
> 
> Development done with QEMU model which will be posted shortly.
> 
> Example:
> 
> $ perf stat -e cxl_pmu_mem0.0/h2d_req_snpcur/ -e cpmu0/h2d_req_snpdata/ -e cpmu0/clock_ticks/ sleep 1
> 
> Performance counter stats for 'system wide':
> 
> 96,757,023,244,321      cxl_pmu_mem0.0/h2d_req_snpcur/
> 96,757,023,244,365      cxl_pmu_mem0.0/h2d_req_snpdata/
> 193,514,046,488,653      cxl_pmu_mem0.0/clock_ticks/
> 
>        1.090539600 seconds time elapsed
> 
> Reviewed-by: Dave Jiang <dave.jiang@xxxxxxxxx>
> Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>

Jonathan, I was awaiting a "perf maintainer ack" before applying this,
only to now realize there is no maintainer entry for drivers/perf/ in
general, only "ARM PMU PROFILING AND DEBUGGING". Were you waiting on any
additional acks from perf folks for this?

If there are no objections I think this can be included in the back half
of the merge window for v6.4, as it stands now I was still awaiting the
final go ahead.