[PATCH v1 0/5] Add PASID support to SMMUv3 unmanaged domains

From: Michael Shavit
Date: Wed May 10 2023 - 16:52:27 EST

Hi all,

This patch series refactors the arm-smmu-v3 driver and implements the
set_dev_pasid functionality for DMA and UNMANAGED iommu domains. As part
of this effort, we also refactor the arm-smmu-v3 driver such that each
iommu domain represent a single address space. In particular, stage 1
domains hold a single ContextDescriptor instead of the entire STE entry.

The refactor is arguably valuable independently from the set_dev_pasid
feature since an iommu_domain is conceptually closer to a single address
space than an entire STE. In addition this unlocks some nice clean-up of
the arm SVA implementation which today piggybacks SVA domains on the
"primary" domain.

This patch series makes some changes to SVA and PCIe, but I haven't
tested those features. The cd table allocations could also be further
optimized for masters that don't support multiple context. However, the
SMMUv3 Nested translation patch series has me worried about this
change. At a glance, it seems like this refactor conflicts with its
proposed uAPI. Is this refactor no longer an appropriate clean-up or
path forward for set_dev_pasid support? Or could a uAPI that only
exposes a single CD instead of the entire STE be an appropriate fit for
the nesting use cases?

Michael Shavit

Link: https://lore.kernel.org/all/CAKHBV24u9b-=cJCF=Kt=3B4hynOyNr6gmi0F6zpO6b1mHc0Z7g@xxxxxxxxxxxxxx
Link: https://lore.kernel.org/all/cover.1683688960.git.nicolinc@xxxxxxxxxx/

Michael Shavit (5):
iommu/arm-smmu-v3: Move cdtable to arm_smmu_master
iommu/arm-smmu-v3: Add has_stage1 field
iommu/arm-smmu-v3: Simplify arm_smmu_enable_ats
iommu/arm-smmu-v3: Keep track of attached ssids
iommu/arm-smmu-v3: Implement set_dev_pasid

.../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 46 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 432 ++++++++++++------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 44 +-
3 files changed, 344 insertions(+), 178 deletions(-)