Re: [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree

From: Jisheng Zhang
Date: Wed May 10 2023 - 20:51:13 EST

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On Thu, May 11, 2023 at 04:44:53AM +0800, Yangtao Li wrote:
> From: Jisheng Zhang <jszhang@xxxxxxxxxx>
>
> Add initial device tree for the TH1520 RISC-V SoC by
> T-HEAD.

It's impolite to randomly jump into and take over other people's patch
series.

>
> Cc: Icenowy Zheng <uwu@xxxxxxxxxx>
> Cc: Wei Fu <wefu@xxxxxxxxxx>
> Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> Signed-off-by: Yangtao Li <frank.li@xxxxxxxx>
> ---
> v2:
> -remove reset-sample
> -convert to use thead,c900-plic
> -add pvt node

No, plz keep the initial soc dtsi as basic/small as possible. You can
add the pvt as an independent patch. But again, don't jump into and take
my patch series.

> -add thermal-zones

ditto

> arch/riscv/boot/dts/thead/th1520.dtsi | 491 ++++++++++++++++++++++++++
> 1 file changed, 491 insertions(+)
> create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> new file mode 100644
> index 000000000000..d1d94098b6bf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -0,0 +1,491 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Alibaba Group Holding Limited.
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@xxxxxxxxxx>
> + * Copyright (C) 2023 Yangtao Li <frank.li@xxxxxxxx>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "thead,th1520";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> +
> + c910_0: cpu@0 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <0>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_1: cpu@1 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <1>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_2: cpu@2 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <2>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_3: cpu@3 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <3>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&c910_0>;
> + };
> +
> + core1 {
> + cpu = <&c910_1>;
> + };
> +
> + core2 {
> + cpu = <&c910_2>;
> + };
> +
> + core3 {
> + cpu = <&c910_3>;
> + };
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <1048576>;
> + cache-sets = <1024>;
> + cache-unified;
> + };
> + };
> +
> + osc: oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "osc_24m";
> + #clock-cells = <0>;
> + };
> +
> + osc_32k: 32k-oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "osc_32k";
> + #clock-cells = <0>;
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + uart_sclk: uart-sclk-clock {
> + compatible = "fixed-clock";
> + clock-output-names = "uart_sclk";
> + #clock-cells = <0>;
> + };
> +
> + pvt_clk: pvt-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <73728000>;
> + clock-output-names = "pvt_clk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + plic: interrupt-controller@ffd8000000 {
> + compatible = "thead,c900-plic";
> + reg = <0xff 0xd8000000 0x0 0x01000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + riscv,ndev = <240>;
> +
> + };
> +
> + clint: timer@ffdc000000 {
> + compatible = "thead,c900-clint";
> + reg = <0xff 0xdc000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>;
> + };
> +
> + uart0: serial@ffe7014000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7014000 0x0 0x4000>;
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart1: serial@ffe7f00000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f00000 0x0 0x4000>;
> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@ffe7f04000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f04000 0x0 0x4000>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gpio2: gpio@ffe7f34000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f34000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio3: gpio@ffe7f38000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f38000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio0: gpio@ffec005000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec005000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@ffec006000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec006000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + uart2: serial@ffec010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xec010000 0x0 0x4000>;
> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + dmac0: dma-controller@ffefc00000 {
> + compatible = "snps,axi-dma-1.01a";
> + reg = <0xff 0xefc00000 0x0 0x1000>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb_clk>, <&apb_clk>;
> + clock-names = "core-clk", "cfgr-clk";
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,axi-max-burst-len = <16>;
> + status = "disabled";
> + };
> +
> + timer0: timer@ffefc32000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32000 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer1: timer@ffefc32014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer2: timer@ffefc32028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer3: timer@ffefc3203c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc3203c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart4: serial@fff7f08000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f08000 0x0 0x4000>;
> + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@fff7f0c000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f0c000 0x0 0x4000>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + timer4: timer@ffffc33000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33000 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer5: timer@ffffc33014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer6: timer@ffffc33028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer7: timer@ffffc3303c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc3303c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ao_gpio0: gpio@fffff41000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff41000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porte: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + pvt: pvt@fffff4e000 {
> + compatible = "moortec,mr75203";
> + reg = <0xff 0xfff4e000 0x0 0x80>,
> + <0xff 0xfff4e080 0x0 0x100>,
> + <0xff 0xfff4e180 0x0 0x680>,
> + <0xff 0xfff4e800 0x0 0x600>;
> + reg-names = "common", "ts", "pd", "vm";
> + clocks = <&pvt_clk>;
> + /* TODO: add reset */
> + #thermal-sensor-cells = <1>;
> + status = "disabled";
> + };
> +
> + ao_gpio1: gpio@fffff52000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff52000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portf: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&pvt 0>;
> +
> + trips {
> + trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + trip1 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> +};
> --
> 2.34.1
>

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