[PATCH v3 1/2] mtd: rawnand: marvell: ensure timing values are written

From: Chris Packham
Date: Wed May 24 2023 - 20:37:45 EST

When new timing values are calculated in marvell_nfc_setup_interface()
ensure that they will be applied in marvell_nfc_select_target() by
clearing the selected_chip pointer.

Fixes: b25251414f6e ("mtd: rawnand: marvell: Stop implementing ->select_chip()")
Suggested-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>

This at least gets me to a point where I can illustrated the problem
reported to me. It appears that despite the chip correctly reporting
support for SDR timing modes up to 4 the observed tWC is 20ns. I've not
seen any actual problem running in this state the only complaint is that
the datasheet says the minimum tWC is 25ns.

If I make a change to my bootloader such that the NAND Clock Frequency
Select bit (0xF2440700:0) to 1 before booting the kernel _and_ I remove
the extra factor of 2 from the period_ns calculation I observe tWC of
about 60ns. If I don't remove the factor of 2 the NAND interface doesn't
work (can't write BBT).

Changes in v3:
- none
Changes in v2:
- reword comment per suggestion from Miquel, add fixes tag

drivers/mtd/nand/raw/marvell_nand.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index afb424579f0b..f1fcf136ad03 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -2457,6 +2457,12 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,

+ /*
+ * Reset nfc->selected_chip so the next command will cause the timing
+ * registers to be updated in marvell_nfc_select_target().
+ */
+ nfc->selected_chip = NULL;
return 0;