[PATCH V2 2/6] clk: qcom: Update l value configuration for lucid ole and evo plls
From: Jagadeesh Kona
Date: Thu May 25 2023 - 13:22:39 EST
For lucid evo and ole pll's the CAL_L, RING_OSC_CAL_L and L_VAL
are part of the same register, hence update the l configuration
value to include these fields across all the chipsets.
Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
---
Changes since V1:
- Newly added.
drivers/clk/qcom/camcc-sm8450.c | 24 ++++++++++++++++--------
drivers/clk/qcom/dispcc-sm8450.c | 10 ++++++----
drivers/clk/qcom/dispcc-sm8550.c | 6 ++++--
drivers/clk/qcom/gpucc-sa8775p.c | 6 ++++--
4 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
index 51338a2884d2..6a5a08f88598 100644
--- a/drivers/clk/qcom/camcc-sm8450.c
+++ b/drivers/clk/qcom/camcc-sm8450.c
@@ -57,7 +57,8 @@ static const struct pll_vco rivian_evo_vco[] = {
static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct alpha_pll_config cam_cc_pll0_config = {
- .l = 0x3e,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044003e,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -128,7 +129,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
};
static const struct alpha_pll_config cam_cc_pll1_config = {
- .l = 0x25,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x00440025,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -199,7 +201,8 @@ static struct clk_alpha_pll cam_cc_pll2 = {
};
static const struct alpha_pll_config cam_cc_pll3_config = {
- .l = 0x2d,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -247,7 +250,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
};
static const struct alpha_pll_config cam_cc_pll4_config = {
- .l = 0x2d,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -295,7 +299,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
};
static const struct alpha_pll_config cam_cc_pll5_config = {
- .l = 0x2d,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -343,7 +348,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
};
static const struct alpha_pll_config cam_cc_pll6_config = {
- .l = 0x2d,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -391,7 +397,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
};
static const struct alpha_pll_config cam_cc_pll7_config = {
- .l = 0x2d,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -439,7 +446,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
};
static const struct alpha_pll_config cam_cc_pll8_config = {
- .l = 0x32,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x00440032,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index adbfd30bfc96..b0f86bd40a80 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -76,11 +76,12 @@ static struct pll_vco lucid_evo_vco[] = {
};
static const struct alpha_pll_config disp_cc_pll0_config = {
- .l = 0xD,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044000d,
.alpha = 0x6492,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
- .config_ctl_hi1_val = 0x32AA299C,
+ .config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
@@ -103,11 +104,12 @@ static struct clk_alpha_pll disp_cc_pll0 = {
};
static const struct alpha_pll_config disp_cc_pll1_config = {
- .l = 0x1F,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044001f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
- .config_ctl_hi1_val = 0x32AA299C,
+ .config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 1e5a11081860..b0d4c623731d 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -76,7 +76,8 @@ static struct pll_vco lucid_ole_vco[] = {
};
static const struct alpha_pll_config disp_cc_pll0_config = {
- .l = 0xd,
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x4444000d,
.alpha = 0x6492,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -103,7 +104,8 @@ static struct clk_alpha_pll disp_cc_pll0 = {
};
static const struct alpha_pll_config disp_cc_pll1_config = {
- .l = 0x1f,
+ /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
+ .l = 0x4444001f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 18d23be8d435..153bf6ecb795 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -46,7 +46,8 @@ static const struct pll_vco lucid_evo_vco[] = {
/* 810MHz configuration */
static struct alpha_pll_config gpu_cc_pll0_config = {
- .l = 0x2a,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x0044002a,
.alpha = 0x3000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
@@ -72,7 +73,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
/* 1000MHz configuration */
static struct alpha_pll_config gpu_cc_pll1_config = {
- .l = 0x34,
+ /* .l includes CAL_L_VAL, L_VAL fields */
+ .l = 0x00440034,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
--
2.40.1