Re: [PATCH v2 2/2] clk: divider: Fix divisions
From: AngeloGioacchino Del Regno
Date: Mon May 29 2023 - 04:51:25 EST
Il 26/05/23 19:10, Sebastian Reichel ha scritto:
The clock framework handles clock rates as "unsigned long", so u32 on
32-bit architectures and u64 on 64-bit architectures.
The current code pointlessly casts the dividend to u64 on 32-bit
architectures and thus pointlessly reducing the performance.
On the other hand on 64-bit architectures the divisor is masked and only
the lower 32-bit are used. Thus requesting a frequency >= 4.3GHz results
in incorrect values. For example requesting 4300000000 (4.3 GHz) will
effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
is a bit of a special case, since that still returns correct values as
long as the parent clock is below 8.5 GHz.
Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>