Re: [PATCH 0/5] MDSS reg bus interconnect

[Dmitry Baryshkov]

On 29/05/2023 12:08, Konrad Dybcio wrote:
> On 29.05.2023 10:47, Dmitry Baryshkov wrote:
> > On 29/05/2023 10:42, Konrad Dybcio wrote:
> > > On 29.05.2023 04:42, Dmitry Baryshkov wrote:
> > > > On Mon, 17 Apr 2023 at 18:30, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote:
> > > > > Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
> > > > > another path that needs to be handled to ensure MDSS functions properly,
> > > > > namely the "reg bus", a.k.a the CPU-MDSS interconnect.
> > > > >
> > > > > Gating that path may have a variety of effects.. from none to otherwise
> > > > > inexplicable DSI timeouts..
> > > > >
> > > > > This series tries to address the lack of that.
> > > > >
> > > > > Example path:
> > > > >
> > > > > interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>;
> > > >
> > > > If we are going to touch the MDSS interconnects, could you please also
> > > > add the rotator interconnect to the bindings?
> > > > We do not need to touch it at this time, but let's not have to change
> > > > bindings later again.
> > > Ack
> >
> > Also, several points noted from the mdss fbdev driver:
> >
> > - All possible clents vote for the low bw setting. This includes DSI, HDMI, MDSS itself and INTF
> As in, "you need NUM_CLIENTS * MIN_VOTE" or as in "any client necessitates
> a vote"?

Each client has separate vote

> > - SMMU also casts such vote, which I do not think should be necessary, unless there is a separate MDSS SMMU?
> There's one on 8996, pre-845 SoCs often have a MMSS MMU, 845 and
> later have a MMSS-specific TBU which (theoretically) requires a
> vote for access to 0x400-0x7ff SIDs

Ack.

> > - PINGPONG cacsts high bw setting for the sake of speeding up the LUT tables if required.
> Hm, I think is would be a separate topic.

I think so. I'd do a single vote from mdp5/dpu1. Then we can cast higher 
vote from PP/DSPP/etc.

--
With best wishes
Dmitry