Re: [PATCH v13 4/6] clk: meson: a1: add Amlogic A1 PLL clock controller driver

From: Martin Blumenstingl
Date: Mon May 29 2023 - 16:23:52 EST

Hello Dmitry,

On Mon, May 29, 2023 at 3:49 PM Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxx> wrote:
> Hello Martin,
> As I promised before, I'm now back with the vendor's reply regarding
> AUDDDS. The information is still incomplete, but I have provided the
> available details below. Please take a look.
Great, thank you for following up!

> AUDDDS is a direct digital synthesizer used as a clock source. It is
> not used as default. You need to modify some clk registers in dts to
> enable it. Basically, it is used for audio.
> In A1 design, you can use AUD DDS as a clock source and it is not
> necessary. It is not used in the Amlogic default setting.
> According to the vendor, it is not necessary and is currently disabled
> by default. While we don't have much information about AUDDDS, the
> vendor suggests that it's not a commonly used clock object in A1
> projects and it may be skipped if not needed.
My goal is to make the dt-bindings match the hardware implementation...

> Based on all above information, I suppose we can skip it now.
...but in this case we simply don't have enough information (other
than some register names and a high level description that it can be
used as a clock) to do that.
I still think we did the best we could for now, so I agree with you:
let's skip it for now (and hope that retrofitting it later - if we
ever need it - won't be a problem).

Best regards,