Re: [PATCH v1] meson saradc: fix clock divider mask length

[Martin Blumenstingl]

Hi George,

On Mon, May 22, 2023 at 5:47 PM Старк Георгий Николаевич
<GNStark@xxxxxxxxxxxxxx> wrote:
>
> Hello Martin
>
> Actually you were right that my patch affects only meson8 family not the all new ones, my bad.
> It's clear from the driver code meson_saradc.c and dts files.
> I've made an experiment on a113l soc - changingclock_rate inmeson_sar_adc_param and measuring adc channel many times
> and with low clockfrequency (priv->adc_clk) time of measurementis high
> and vice versa. ADC_CLK_DIV field in SAR_ADC_REG3 is always zero.
Thanks for sharing your findings!

> I need to get s805 (meson8) board for example and made experiment on it.
If you don't find any Meson8 (S802)/Meson8b (S805) or Meson8m2 (S812)
board then please provide the code that you used for your experiment
as a patch so I can give it a try on my Odroid-C1 (Meson8b).


Best regards,
Martin