Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR

[Geert Uytterhoeven]

On Tue, May 30, 2023 at 10:13 AM Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
> On Mon, Mar 7, 2022 at 11:15 PM Will Deacon <will@xxxxxxxxxx> wrote:
> > On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> > > When a IAR register read races with a GIC interrupt RELEASE event,
> > > GIC-CPU interface could wrongly return a valid INTID to the CPU
> > > for an interrupt that is already released(non activated) instead of 0x3ff.
> > >
> > > As a side effect, an interrupt handler could run twice, once with
> > > interrupt priority and then with idle priority.
> > >
> > > [...]
> >
> > Applied to arm64 (for-next/errata), thanks!
> >
> > [1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
> >       https://git.kernel.org/arm64/c/24a147bcef8c
>
> This workaround is now enabled on R-Car V4H:
>
>     GIC: enabling workaround for GICv3: Cavium erratum 38539
>
> which is not a Cavium SoC. Is this expected?
> Thanks!

Please ignore, wrong thread. Sorry for the fuzz.
(note to myself: do not trust Gmail search to match on all search parameters)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds